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-rw-r--r--UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf26
-rw-r--r--UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S22
2 files changed, 48 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
new file mode 100644
index 0000000000..8130430310
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVFpuLib/BaseRiscVFpuLib.inf
@@ -0,0 +1,26 @@
+## @file
+# RISC-V FPU library.
+#
+# Copyright (c) 2024, Canonical Services Ltd
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = BaseRiscVFpuLib
+ FILE_GUID = e600fe4d-8595-40f3-90a0-5f043ce155c2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFpuLib
+
+[Sources]
+ RiscVFpuCore.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S
new file mode 100644
index 0000000000..b439af4e42
--- /dev/null
+++ b/UefiCpuPkg/Library/BaseRiscVFpuLib/RiscVFpuCore.S
@@ -0,0 +1,22 @@
+/** @file
+*
+* Copyright (c) 2024, Canonical Services Ltd
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/BaseRiscVFpuLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+//
+// Initialize floating point unit
+//
+ASM_FUNC (RiscVInitializeFpu)
+ csrr a0, CSR_SSTATUS
+ li a1, MSTATUS_FS
+ or a0, a0, a1
+ csrw CSR_SSTATUS, a0
+ csrw CSR_FCSR, x0
+ li a0, 0
+ ret