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Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c86
1 files changed, 44 insertions, 42 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index ce7afce6d4..00a284c369 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "PiSmmCpuDxeSmm.h"
-EFI_PHYSICAL_ADDRESS mGdtBuffer;
-UINTN mGdtBufferSize;
+EFI_PHYSICAL_ADDRESS mGdtBuffer;
+UINTN mGdtBufferSize;
-extern BOOLEAN mCetSupported;
-extern UINTN mSmmShadowStackSize;
+extern BOOLEAN mCetSupported;
+extern UINTN mSmmShadowStackSize;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;
-UINT32 mCetPl0Ssp;
-UINT32 mCetInterruptSsp;
-UINT32 mCetInterruptSspTable;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;
+UINT32 mCetPl0Ssp;
+UINT32 mCetInterruptSsp;
+UINT32 mCetInterruptSspTable;
UINTN mSmmInterruptSspTables;
@@ -33,14 +33,14 @@ UINTN mSmmInterruptSspTables;
VOID
EFIAPI
InitializeIdtIst (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN UINT8 Ist
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN UINT8 Ist
)
{
IA32_IDT_GATE_DESCRIPTOR *IdtGate;
- IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
- IdtGate += ExceptionType;
+ IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
+ IdtGate += ExceptionType;
IdtGate->Bits.Reserved_0 = Ist;
}
@@ -59,34 +59,34 @@ InitGdt (
OUT UINTN *GdtStepSize
)
{
- UINTN Index;
- IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
- UINTN TssBase;
- UINTN GdtTssTableSize;
- UINT8 *GdtTssTables;
- UINTN GdtTableStepSize;
+ UINTN Index;
+ IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
+ UINTN TssBase;
+ UINTN GdtTssTableSize;
+ UINT8 *GdtTssTables;
+ UINTN GdtTableStepSize;
//
// For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
// on each SMI entry.
//
GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
- mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
- GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
+ mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
+ GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
- mGdtBuffer = (UINTN)GdtTssTables;
+ mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
- CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
+ CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
//
// Fixup TSS descriptors
//
- TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
- GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
- GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
- GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
+ TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
+ GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
+ GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
+ GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) || ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported)) {
@@ -118,15 +118,17 @@ GetProtectedModeCS (
AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
- if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {
+ if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break;
}
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -171,9 +173,9 @@ InitShadowStack (
IN VOID *ShadowStack
)
{
- UINTN SmmShadowStackSize;
- UINT64 *InterruptSspTable;
- UINT32 InterruptSsp;
+ UINTN SmmShadowStackSize;
+ UINT64 *InterruptSspTable;
+ UINT32 InterruptSsp;
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
@@ -188,14 +190,15 @@ InitShadowStack (
//
SmmShadowStackSize += EFI_PAGES_TO_SIZE (1);
}
- mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
+
+ mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (mSmmInterruptSspTables == 0) {
- mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
+ mSmmInterruptSspTables = (UINTN)AllocateZeroPool (sizeof (UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
ASSERT (mSmmInterruptSspTables != 0);
DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));
}
@@ -209,17 +212,16 @@ InitShadowStack (
// Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.
// According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned.
//
- InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - (sizeof(UINT64) * 4)) & ~0x1f);
- *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
- mCetInterruptSsp = InterruptSsp - sizeof(UINT64);
+ InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - (sizeof (UINT64) * 4)) & ~0x1f);
+ *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof (UINT64) * 4) | 0x2;
+ mCetInterruptSsp = InterruptSsp - sizeof (UINT64);
- mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);
- InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
- InterruptSspTable[1] = mCetInterruptSsp;
+ mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof (UINT64) * 8 * CpuIndex);
+ InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
+ InterruptSspTable[1] = mCetInterruptSsp;
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable, 4);
DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));
}
}
-
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 12:59:44 +0000