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* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-294-0/+39
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* MdePkg/ProcessorBind.h AARCH64: limit MAX_ADDRESS to 48 bitsArd Biesheuvel2018-11-291-2/+2
| | | | | | | | | | | | AArch64 supports the use of more than 48 bits for physical and/or virtual addressing, but only if the page size is set to 64 KB, which is not supported by UEFI. So redefine MAX_ADDRESS to cover only 48 address bits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmVirtPkg/QemuVirtMemInfoLib: remove 1:1 mapping of top of PA rangeArd Biesheuvel2018-11-295-97/+5
| | | | | | | | | | | | | | | | | Currently, we map DRAM as EFI_MEMORY_WB, and the remainder of the entire virtual address space is mapped with EFI_MEMORY_UC attributes, regardless of whether any devices actually reside there. Now that we are relaxing the address space limit to more than 40 bits, mapping all that address space actually takes up more space in page tables than we have so far made available as temporary RAM. So let's get rid of the mapping rather than increasing the available RAM, given that the mapping is not particularly useful anyway. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg/FdtPciHostBridgeLib: map ECAM and I/O spaces in GCD memory mapArd Biesheuvel2018-11-292-1/+46
| | | | | | | | | | | | | | | | | | | | Up until now, we have been getting away with not declaring the ECAM and translated I/O spaces at all in the GCD memory map, simply because we map the entire address space with device attributes in the early PEI code, and so the ECAM space will be mapped wherever it ends up. Now that we are about to make changes to how ArmVirtQemu reasons about the size of the address space, it would be better to get rid of this mapping of the entire address space, since it can get arbitrarily large without real benefit. So start by mapping the ECAM and translated I/O spaces explicitly, instead of relying on the early PEI mapping. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* EmbeddedPkg/PrePiHobLib: drop CreateHobList() from libraryArd Biesheuvel2018-11-293-62/+0
| | | | | | | | | | Drop the declaration and the implementation of CreateHoblist(), which is not used anywhere. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* EmbeddedPkg/TemplateSec: remove unused moduleArd Biesheuvel2018-11-292-141/+0
| | | | | | | | | | Remove this module: it is unused, and should not be used as an example going forward. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* Maintainers.txt: Update MdeModulePkg maintainersStar Zeng2018-11-291-1/+2
| | | | | | | | | | | | | As Star has some other focus, change Star from maintainer to reviewer, Jian will be the first maintainer, and add Hao as the second maintainer. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Acked-by: Hao Wu <hao.a.wu@intel.com> Acked-by: Jian J Wang <jian.j.wang@intel.com>
* Maintainers.txt: Update FmpDevicePkg maintainerStar Zeng2018-11-291-1/+1
| | | | | | | | | | | As Star has some other focus, remove Star and add Liming as the FmpDevicePkg maintainer. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Acked-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/BaseSortLib: Enable for all module typesJeff Brasen2018-11-291-2/+2
| | | | | | | | | | Expose BaseSortLib for use in SEC and PEI phases. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* EmbeddedPkg/PrePiMemoryAllocationLib: Added AllocateZeroPool()Jeff Brasen2018-11-291-0/+32
| | | | | | | | | | This function is exposed by the MemoryAllocationLib header. An AllocateZeroPool() function has been added to fix modules depending on this library and this function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* BaseTools Script: Update ConvertFceToStructurePcd to report warning messagesLiming Gao2018-11-291-1/+1
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1297 When the header files are not found for the used C structure, this script will report the warning, let user know there is no header file to define C structure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wang BinX A <binx.a.wang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* Maintainers.txt: Add the rule to hand over the package maintain roleLiming Gao2018-11-291-0/+5
| | | | | | | | | In V2, change his to the, and add new maintainers follow up. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg: fix StandaloneMmMmuLib subdirectory caseLeif Lindholm2018-11-272-1/+1
| | | | | | | | | While this isn't the only Aarch64 directory in the tree, let's keep from adding more of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmPkg.dsc: move ArmMmuStandaloneMmLib.inf to AARCH64 sectionArd Biesheuvel2018-11-271-1/+1
| | | | | | | | | ArmMmuStandaloneMmLib.inf cannot be built for ARM so move it to the [Components.AARCH64] section in ArmPkg.dsc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-275-0/+265
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add MM interface SVC return codes.Achin Gupta2018-11-271-0/+7
| | | | | | | | | This patch adds the Management Mode(MM) - Secure Partition Manager(SPM) SVC return codes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Fix the SPM version SVC IDSughosh Ganu2018-11-271-1/+1
| | | | | | | | | The MM_VERSION SMC call uses SMC32 calling convention. Fix the macro to reflect the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Drivers: Add EFI_MM_COMMUNICATION_PROTOCOL DXE driver.Achin Gupta2018-11-273-0/+456
| | | | | | | | | | | | | | | | | | | | PI v1.5 Specification Volume 4 defines Management Mode Core Interface and defines EFI_MM_COMMUNICATION_PROTOCOL. This protocol provides a means of communicating between drivers outside of MM and MMI handlers inside of MM. This patch implements the EFI_MM_COMMUNICATION_PROTOCOL DXE runtime driver for AARCH64 platforms. It uses SMCs allocated from the standard SMC range defined in DEN0060A_ARM_MM_Interface_Specification.pdf to communicate with the standalone MM environment in the secure world. This patch also adds the MM Communication driver (.inf) file to define entry point for this driver and other compile related information the driver needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add PCDs needed for MM communication driver.Achin Gupta2018-11-271-0/+3
| | | | | | | | | | This patch defines PCDs to describe the base address and size of communication buffer between normal world (uefi) and standalone MM environment in the secure world. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/NorFlashPlatformLib: remove unused Guid member from structArd Biesheuvel2018-11-271-1/+0
| | | | | | | | | | | We no longer use per-instance GUIDs to identify NOR flash banks so there is no longer a need to define them. Drop the Guid member from the NOR_FLASH_DESCRIPTION type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* MdeModulePkg PCD: Add DynamicEx PcdVpdBaseAddress64 for non SPI platformLiming Gao2018-11-278-4/+54
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1356 Current PcdVpdBaseAddress is 32bit static Pcd. NON SPI platform needs to configure it as Dynamic PCD. Emulator platform (such as NT32) may set its value to 64bit address. To meet with this usage, 64bit DynamicEx PcdVpdBaseAddress64 is introduced. If its value is not zero, it will be used. If its value is zero, static PcdVpdBaseAddress will be used. When NON SPI platform enables VPD PCD, they need to set PcdVpdBaseAddress64. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Dandan Bi <dandan.bi@intel.com>
* OvmfPkg: Don't include TftpDynamicCommand in XCODE5 tool chainLiming Gao2018-11-276-0/+12
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1355 XCODE doesn't support HII resource section. TftpDynamicCommand driver depends on HII resource section. To let OvmfPkg boot to shell on XCODE5 tool chain, don't include TftpDynamicCommand driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg ACPI: fix the typos in Acpi61.h and Acpi62.hGary Lin2018-11-272-2/+2
| | | | | | | | | | | | | The GUID for VIRTUAL_CD_REGION_PERSISTENT was using the closing square bracket mistakenly. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ArmVirtPkg/NorFlashQemuLib: discover NOR flash banks dynamicallyArd Biesheuvel2018-11-262-21/+69
| | | | | | | | | | | | | | | | | | | | | | | | NorFlashQemuLib is one of the last remaining drivers in ArmVirtPkg that are not based on the device tree received from QEMU. For ArmVirtQemu, this does not really matter, given that the NOR flash banks are always the same: the PEI code is linked to execute in place from flash bank #0, and the fixed varstore PCDs refer to flash bank #1 directly. However, ArmVirtQemuKernel can execute at any offset, permitting it to be used as an intermediary loader when running QEMU with secure world emulation enabled, in which case NOR flash bank #0 is secure only and contains the secure world firmware. In this case, NorFlashQemuLib should not expose the first flash bank at all. To prevent introducing too much internal knowledge about which flash bank is accessible under which circumstances, let's switch to using the DTB to decide which flash banks to expose to the NOR flash driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg/FdtClientDxe: take DT node 'status' properties into accountArd Biesheuvel2018-11-261-5/+33
| | | | | | | | | | | | DT has a [pseudo-]standardized 'status' property that can be set on any node, and which signifies that a node should be treated as absent unless it is set to 'ok' or 'okay'. So take this into account when iterating over nodes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ArmPlatformPkg/NorFlashDxe: use one GUID plus index to identify flash banksArd Biesheuvel2018-11-262-3/+4
| | | | | | | | | | | | | | | | | | | | | | Currently, each flash bank controlled by ArmPlatformPkg/NorFlashDxe has its own VendorHw GUID, and instances of NorFlashPlatformLib describe each bank to the driver, along with the GUID for each. This works ok for bare metal platforms, but it would be useful for virtual platforms if we could obtain this information from a device tree, which would require us to invent GUIDs on the fly, given that the 'cfi-flash' binding does not include a GUID. So instead, let's switch to a single GUID for all flash banks, and update the driver's device path handling to include an index to identify each bank uniquely. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* ArmPlatformPkg/NorFlashDxe: prepare for devicepath format changeArd Biesheuvel2018-11-262-3/+8
| | | | | | | | | | | | | | | A subsequent patch will change the layout of devicepath nodes produced by this driver. In preparation, make some tweaks to the code to use a packed struct for the devicepath and to pass the device index to NorFlashCreateInstance(). These are cosmetic changes only, the resulting binaries should be identical. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* ArmPkg: remove now unused BsdLib.hArd Biesheuvel2018-11-261-212/+0
| | | | | | | | | The last remaining users of the BdsLib.h header reside in the edk2-platforms tree, and so it has been copied there. This allows us to remove the original from ArmPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* IntelFsp2WrapperPkg: Fix constant if statements issueChasel, Chiu2018-11-262-2/+2
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1351 Internal code quality scanning found 2 constant if statements related to FixedPcdGet8 () usage. Since the PCD can be PatchableInModule too, it should be changed to PcdGet8 () to fix this issue. Test: Verified on internal platform and booted successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* IntelFsp2WrapperPkg: Fix line ending format issueChasel, Chiu2018-11-265-43/+43
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1352 Fixed line ending format wrong issues on some files. Test: Verified building successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Wu Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/LockboxNullLib: clean up INF file.Jiewen Yao2018-11-261-1/+1
| | | | | | | | | Remove unused module type restriction for NULL instance. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* NetworkPkg/IScsiDxe: add debug logs for failed SetVariable attemptsVijayenthiran Subramaniam2018-11-231-0/+8
| | | | | | | | | | Add debug messages for failed attempts to write to a variable. Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
* Vlv2TbltDevicePkg:Fix build and boot failure of Minnowboard Max platform.zwei42018-11-234-3/+6
| | | | | | | | | | | | Remove the duplicated IScsiDxe driver from FDF; Add required shell libraries; Update SYSTEM_CONFIGURATION data structure. Test: Install and boot Windows 10. Cc: Zailiang Sun <zailiang.sun@intel.com> Cc: Yi Qian <yi.qian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Wei <david.wei@intel.com>
* MdeModulePkg/Variable: add debug logs in VariableServiceSetVariableVijayenthiran Subramaniam2018-11-231-0/+30
| | | | | | | | | | | | | | Print debug messages if size of the VariableName plus DataSize exceeds Max(Auth|Voltaile)VariableSize bytes. The messages will be useful if any platform specific value of Max(Auth|Voltaile)VariableSize PCDs have to be changed. Cc: Star Zeng <star.zeng@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ShellPkg: Remove ShellPkg wrapper header filesShenglei Zhang2018-11-224-82/+0
| | | | | | | | | | | | | | These wrapper header files are not referenced by all open source, so they are removed. https://bugzilla.tianocore.org/show_bug.cgi?id=158 Cc: Jaben Carsey <jaben.carsey@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
* ArmPkg/ArmSmcPsciResetSystemLib: add missing call to ExitBootServices()Ard Biesheuvel2018-11-216-6/+187
| | | | | | | | | | | | | | | | | | | | Our poor man's implementation of EnterS3WithImmediateWake () currently sets a high TPL level to disable interrupts, and simply calls the PEI entrypoint again after disabling the MMU. Unfortunately, this is not sufficient: DMA capable devices such as network controllers or USB controllers may still be enabled and writing to memory, e.g., in response to incoming network packets. So instead, do the full ExitBootServices() dance: allocate space and get the memory map, call ExitBootServices(), and in case it fails, get the memory map again and call ExitBootServices() again. This ensures that all cleanup related to DMA capable devices is performed before doing the warm reset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* Maintainers.txt: update Vlv2*Pkg maintainers.Sun, Zailiang2018-11-211-4/+4
| | | | | | | Cc: David Wei <david.wei@intel.com> Cc: Yi Qian <yi.qian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zailiang Sun <zailiang.sun@intel.com>
* MdePkg: Check input Ptrs in GetSectionFromAnyFvByFileTypeDandan Bi2018-11-211-0/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1337 In function GetSectionFromAnyFvByFileType, the input parameter "Buffer" and "size" should not be NULL, so add ASSERT here to avoid any checker report that the NULL pointer may be used. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: check Length para before use in DevPathToTextUsbWWIDDandan Bi2018-11-211-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1336 In function DevPathToTextUsbWWID, the Length parameter is used without check. This patch is to add check before using it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdeModulePkg/DisplayEngine: Remove useless NULL ptr check for NewPosDandan Bi2018-11-211-1/+2
| | | | | | | | | | | | | | | | | | | In function UiDisplayMenu, the NewPos ptr which used to point to the highlight menu entry. It will always point to the menu entry which need to be highlighted or the gMenuOption menu if the highlight menu is not found. So we can remove the NULL ptr check for NewPos in this function. And add the ASSERT code to avoid if any false positive reports of NULL pointer dereference issue raised from static analysis. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* SecurityPkg: Update TCG PFP spec revision.Zhang, Chao B2018-11-214-6/+10
| | | | | | | | | | | | | UEFI TCG has aligned with TCG PFP 1.03 v51 along with Errata Version 1.0. Update spec version accordingly. Spec Link: https://trustedcomputinggroup.org/wp-content/uploads/PC-ClientSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-Firmware-Profile-for-TPM-2-0-v1p03_r51-errata-v1p0_170426.pdf Cc: Yao Jiewen <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhang, Chao B <chao.b.zhang@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
* OvmfPkg: simply use the Bochs interface for vmsvgayuchenlin2018-11-203-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | BAR | std vga | vmsvga --------------------------------- 0 | Framebuffer | I/O space 1 | Reserved | Framebuffer 2 | MMIO | FIFO - We cannot recognize VMW SVGA as BOCHS because that would confuse the IsQxl setting in QemuVideoControllerDriverStart(), - We cannot recognize VMW SVGA as BOCHS_MMIO because BAR2 on VMW SVGA is not the BOCHS MMIO BAR (we can only use port IO). Therefore the list of reasons for which we should introduce QEMU_VIDEO_VMWARE_SVGA should name three reasons: (1) Get framebuffer from correct PCI BAR (2) Prevent using BAR2 for MMIO (3) Prevent mis-recognizing VMW SVGA as QXL Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: yuchenlin <yuchenlin@synology.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* Revert "OvmfPkg: VMWare SVGA display device register definitions"yuchenlin2018-11-201-104/+0
| | | | | | | | | | | | | This reverts commit 9bcca53fe466cdff397578328d9d87d257aba493. We reverted VMWare SVGA driver. We don't need these definitions too. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: yuchenlin <yuchenlin@synology.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 328409ce8de7f318ee9c929b64302bd361cd1dbd) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* Revert "OvmfPkg/QemuVideoDxe: Helper functions for unaligned port I/O."yuchenlin2018-11-206-359/+0
| | | | | | | | | | | | | | | | | This reverts commit 05a5379458725234de8a05780fcb5da2c12680e4. The VMWare SVGA display device implemented by Qemu (-vga vmware) uses an I/O-type BAR which is laid out such that some register offsets are not aligned to the read/write width with which they are expected to be accessed. However, we reverted the initialization of VMWare SVGA device, we don't need such unaligned I/O. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: yuchenlin <yuchenlin@synology.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 438ada5aa5a1174940795678c2dae07cde8f3869) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* Revert "OvmfPkg/QemuVideoDxe: VMWare SVGA device support"yuchenlin2018-11-204-379/+7
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit c137d95081690d4877fbeb5f1856972e84ac32f2. The VMWare SVGA model now -- since commit 104bd1dc70 in QEMU -- falls back to stdvga (that is, Bochs) if we don't setup VMWare SVGA FIFO. To simplify QemuVideoDxe, we don't intend to implement the VMWare SVGA FIFO setup feature. It means our current VMW SVGA driver code is basically dead. To simplify the problem, we will replace the old VMWare SVGA driver to Bochs interface. It should work on all QEMU version. The first step for using Bochs interface is to revert old driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: yuchenlin <yuchenlin@synology.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 98856a724c2acdc0094220d4de615a557dad0f88) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* Revert "OvmfPkg/QemuVideoDxe: list "UnalignedIoInternal.h" in the INF file"yuchenlin2018-11-201-1/+0
| | | | | | | | | | | | | | | | | This reverts commit b2959e9f1a57279506ca46d56bc424fd7fa6b62a. The VMWare SVGA display device implemented by Qemu (-vga vmware) uses an I/O-type BAR which is laid out such that some register offsets are not aligned to the read/write width with which they are expected to be accessed. However, we will revert the initialization of VMWare SVGA device later, we don't need such unaligned I/O. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: yuchenlin <yuchenlin@synology.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit e038bde2679bbd200086c25ab43090ad3b8b25a3) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequencyMarcin Wojtas2018-11-207-22/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq field value of the Capability Register 1 is zero, the clock frequency must be obtained via another method. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255MHz. In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient to be used for setting the clock speed in SdMmcHcClockSupply function. This patch adds new UINT32 array ('BaseClkFreq[]') to SD_MMC_HC_PRIVATE_DATA structure for specifying the input clock speed for each slot of the host controller. All routines that are used for clock configuration are updated accordingly. This patch also adds new IN OUT BaseClockFreq field in the Capability callback of the SdMmcOverride, protocol which allows to update BaseClkFreq value. The patch reuses original commit from edk2-platforms: 20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock frequency") Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverrideTomasz Michalec2018-11-203-4/+46
| | | | | | | | | | | | | Some SD Host Controlers need to do additional operations after clock frequency switch. This patch add new callback type to NotifyPhase of the SdMmcOverride protocol. It is called after SdMmcHcClockSupply. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocolTomasz Michalec2018-11-205-60/+181
| | | | | | | | | | | | | | | Some SD Host Controllers use different values in Host Control 2 Register to select UHS Mode. This patch adds a new UhsSignaling type routine to the NotifyPhase of the SdMmcOverride protocol. UHS signaling configuration is moved to a common, default routine (SdMmcHcUhsSignaling). After it is executed, the protocol producer can override the values if needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhaseMarcin Wojtas2018-11-202-5/+11
| | | | | | | | | | | | | In order to ensure bigger flexibility in the NotifyPhase routine of the SdMmcOverride protocol, enable using an optional phase-specific data. This will allow to exchange more information between the protocol producer driver and SdMmcPciHcDxe in the newly added callbacks. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 12:32:11 +0000