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* OvmfPkg/BaseMemEncryptSevLib: remove Flush parameterBrijesh Singh2021-05-2910-62/+21
| | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The Flush parameter is used to provide a hint whether the specified range is Mmio address. Now that we have a dedicated helper to clear the memory encryption mask for the Mmio address range, its safe to remove the Flush parameter from MemEncryptSev{Set,Clear}PageEncMask(). Since the address specified in the MemEncryptSev{Set,Clear}PageEncMask() points to a system RAM, thus a cache flush is required during the encryption mask update. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-14-brijesh.singh@amd.com>
* OvmfPkg/TpmMmioSevDecryptPei: use MemEncryptSevClearMmioPageEncMask()Brijesh Singh2021-05-291-3/+2
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask for the Mmio address range. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-13-brijesh.singh@amd.com>
* OvmfPkg/QemuFlashFvbServicesRuntimeDxe: use Mmio helper to clear enc maskBrijesh Singh2021-05-292-6/+4
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask for the Mmio address range. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-12-brijesh.singh@amd.com>
* OvmfPkg/AmdSevDxe: use MemEncryptSevClearMmioPageEncMask() to clear EncMaskBrijesh Singh2021-05-291-6/+4
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Use the MemEncryptSevClearMmioPageEncMask() to clear memory encryption mask for the Mmio and NonExistent address range. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-11-brijesh.singh@amd.com>
* OvmfPkg/BaseMemEncryptSevLib: introduce MemEncryptSevClearMmioPageEncMask()Brijesh Singh2021-05-296-0/+175
| | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The MemEncryptSevClearMmioPageEncMask() helper can be used for clearing the memory encryption mask for the Mmio region. The MemEncryptSevClearMmioPageEncMask() is a simplified version of MemEncryptSevClearPageEncMask() -- it does not flush the caches after clearing the page encryption mask. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-10-brijesh.singh@amd.com>
* MdePkg/BaseLib: add support for RMPADJUST instructionTom Lendacky2021-05-294-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The RMPADJUST instruction will be used by the SEV-SNP guest to modify the RMP permissions for a guest page. See AMD APM volume 3 for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-9-brijesh.singh@amd.com>
* MdePkg/BaseLib: add support for PVALIDATE instructionBrijesh Singh2021-05-294-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The PVALIDATE instruction validates or rescinds validation of a guest page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS bits OF, ZF, AF, PF and SF are set based on this return code. If the instruction completed succesfully, the rFLAGS bit CF indicates if the contents of the RMP entry were changed or not. For more information about the instruction see AMD APM volume 3. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macros for SNP AP creationTom Lendacky2021-05-291-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled in the guest VM. See the GHCB specification, Table 5 "List of Supported Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details. While at it, define the VMSA state save area that is required for creating the AP. The save area format is defined in AMD APM volume 2, Table B-4 (there is a mistake in the table that defines the size of the reserved area at offset 0xc8 as a dword, when it is actually a word). The format of the save area segment registers is further defined in AMD APM volume 2, sections 10 and 15.5. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com> [lersek@redhat.com: fix typo in BZ reference]
* MdePkg/Register/Amd: define GHCB macro for the Page State ChangeBrijesh Singh2021-05-292-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The Page State Change NAE exit will be used by the SEV-SNP guest to request a page state change using the GHCB protocol. See the GHCB spec section 4.1.6 and 2.3.1 for more detail on the structure definitions. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-6-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macro for Register GPA structureBrijesh Singh2021-05-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 An SEV-SNP guest is required to perform the GHCB GPA registration. See the GHCB specification for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-5-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macros for hypervisor feature detectionBrijesh Singh2021-05-292-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces advertisement of features that are supported by the hypervisor. See the GHCB spec section 2.2 for an additional details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-4-brijesh.singh@amd.com>
* MdePkg/Register/Amd: realign macros with more space for future expansionBrijesh Singh2021-05-292-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of the GHCB spec introduces several new SNP-specific NAEs. Unfortunately, the names for those NAEs break the alignment. Add some white spaces so that the SNP support patches do not break the alignment. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
* MdePkg/Register/Amd: expand the SEV MSR to include the SNP definitionBrijesh Singh2021-05-291-1/+6
| | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
* UefiCpuPkg/MpInitLib: Allocate a separate SEV-ES AP reset stack areaLendacky, Thomas2021-05-293-18/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3324 The SEV-ES stacks currently share a page with the reset code and data. Separate the SEV-ES stacks from the reset vector code and data to avoid possible stack overflows from overwriting the code and/or data. When SEV-ES is enabled, invoke the GetWakeupBuffer() routine a second time to allocate a new area, below the reset vector and data. Both the PEI and DXE versions of GetWakeupBuffer() are changed so that when PcdSevEsIsEnabled is true, they will track the previous reset buffer allocation in order to ensure that the new buffer allocation is below the previous allocation. When PcdSevEsIsEnabled is false, the original logic is followed. Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Marvin Häuser <mhaeuser@posteo.de> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <3cae2ac836884b131725866264e0a0e1897052de.1621024125.git.thomas.lendacky@amd.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* Maintainers.txt: add Sami Mujawar as top-level ArmVirtPkg reviewerLaszlo Ersek2021-05-291-10/+1
| | | | | | | | | | | | | | | | | | | | | | For distributing ArmVirtPkg patch review tasks better, move Sami Mujawar from the "ArmVirtPkg: Kvmtool" section to the top-level "ArmVirtPkg" section. Given that "ArmVirtPkg: Kvmtool" remains without a specific "R" role, remove "ArmVirtPkg: Kvmtool" altogether. Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Julien Grall <julien@xen.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210514114857.12286-1-lersek@redhat.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmGic: Fix maximum number of interrupts in GICv3edk2-stable202105Andreas Sandberg2021-05-271-2/+9
| | | | | | | | | | | | | | | | | | | Bugzilla: 3415 (https://bugzilla.tianocore.org/show_bug.cgi?id=3415) The GICv3 architecture supports up to 1020 ordinary interrupt lines. The actual number of interrupts supported is described by the ITLinesNumber field in the GICD_TYPER register. The total number of implemented registers is normally calculated as 32*(ITLinesNumber+1). However, maximum value (0x1f) is a special case since that would indicate that 1024 interrupts are implemented. Add handling for this special case in ArmGicGetMaxNumInterrupts. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Joey Gouly <joey.gouly@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* MdeModulePkg/VariableLock: downgrade compatibility warnings to DEBUG_WARNLaszlo Ersek2021-05-231-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a18a9bde36d2 ("MdeModulePkg/Variable/RuntimeDxe: Restore Variable Lock Protocol behavior", 2020-12-15), for bug 3111, added two such sets of debug messages that: (a) are relevant for developers, (b) yet should not necessarily poke end-users, because no functionality suffers in practice. Both message sets are in function VariableLockRequestToLock(): the first is a generic interface deprecation warning; the second is the double-locking situation, which we permit for compatibility (return status EFI_SUCCESS). Both message sets should be emitted with the DEBUG_WARN mask, not the most serious DEBUG_ERROR mask. On some platforms, the serial console carries both terminal traffic, and grave (DEBUG_ERROR-only) log messages. On such platforms, both message sets may be perceived as a nuisance by end-users, as there is nothing they can do, and there's nothing they *should* do -- in practice, nothing malfunctions. (Such a platform is ArmVirtQemu, built with "-D DEBUG_PRINT_ERROR_LEVEL=0x80000000".) Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3410 Fixes: a18a9bde36d2ffc12df29cdced1efa1f8f9f2021 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210521204037.11980-1-lersek@redhat.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/PlatformDriOverrideDxe: Fix overflow condition checkLi, Walon2021-05-211-1/+1
| | | | | | | | Code mistake, VariableIndex is smaller normally than buffer+buffersize so should not break loop. Signed-off-by: Walon Li <walon.li@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools: build: Set ReturnCode on POSTBUILD failGarrett Kirkendall2021-05-211-0/+1
| | | | | | | | | | | | | | | When build.by POSTBUILD handling section returns other than 0, set ReturnCode to POSTBUILD_ERROR so build.py exits with return code other than 0. Fix for https://bugzilla.tianocore.org/show_bug.cgi?id=1977 Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* CryptoPkg/BaseCryptLib: Fix possible uninitialized useSergei Dmitrouk2021-05-192-0/+2
| | | | | | | | | | | | `Result` can be used uninitialized in both functions after following either first or second `goto` statement. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* MdeModulePkg/PciBusDxe: Fix possible uninitialized useSergei Dmitrouk2021-05-191-3/+2
| | | | | | | | | | | If the function gets invalid value for the `ResizableBarOp` parameter and asserts are disabled, `Bit` can be used uninitialized. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* ShellPkg/HttpDynamicCommand: Fix possible uninitialized useSergei Dmitrouk2021-05-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | `Status` can be used uninitialized: /* Evaluates to FALSE */ if (ShellGetExecutionBreakFlag ()) { Status = EFI_ABORTED; break; } /* Evaluates to FALSE */ if (!Context->ContentDownloaded && !Context->ResponseToken.Event) { Status = ...; ASSERT_EFI_ERROR (Status); } else { ResponseMessage.Data.Response = NULL; } /* UNINITIALIZED USE */ if (EFI_ERROR (Status)) { break; } Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg: Retrieve boot manager menu from any fvZhiguang Liu2021-05-181-4/+5
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3384 Currently, UefiBootManagerLib has the below assumption: Assume the BootManagerMenuFile is in the same FV as the module links to this library. It has some limitation now, so remove the assumption. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitationRay Ni2021-05-181-8/+18
| | | | | | | | | | | | | 5-level paging can be enabled on CPU which supports up to 52 physical address size. But when the feature was enabled, the 48 address size limit was not removed and the 5-level paging testing didn't access address >= 2^48. So the issue wasn't detected until recently an address >= 2^48 is accessed. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* IntelFsp2Pkg: YAML script bug fixLoo, Tung Lun2021-05-182-3/+11
| | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3395 This patch fixes the issue observed during BSF file to YAML file conversion. It also addresses the issue during multibyte array data conversion check, for example the data representation of 0xFFFF instead of 0xFF, 0xFF would be thrown exception "Array size is not proper" without this patch. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* BaseTools: Add DTCPP_FLAGS for GCC5 RISCV64 toolchainDaniel Schaefer2021-05-171-0/+1
| | | | | | | | | | | | | | Some/all platforms are going to require EDK2 to build a device tree and use it in the early stages of boot. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Abner Chang <abner.chang@hpe.com> Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseTools/Brotli: Fix compressed data loss issueChen, Christine2021-05-171-23/+38
| | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2946 Currenly, when using the Brotli tool to compress data, the output compressed binary file does not record complete compressed data when size of input file is too large, which makes the data loss and will trigger decompress-check issue. The Brotli document mentioned: The brotli tool use BrotliEncoderCompressStream method to compresses input stream to output stream. Under some circumstances (e.g. lack of output stream capacity) the BrotliEncoderOperation would require several calls to BrotliEncoderCompressStream. The method must be called again until both input stream is depleted and encoder has no more output after the method is called. This patch fixes this issue based on the Brotli document. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* MdeModulePkg: Fix various typosRebecca Cran2021-05-1712-35/+35
| | | | | | | | Fix various typos throughout MdeModulePkg. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuExceptionHandler: Add missing comma to exception name arrayLendacky, Thomas2021-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3373 An update to expand the mExceptionNameStr array failed to add a comma after original last entry, therefore causing the #CP name to have extra incorrect characters and the remaining entries to be indexed incorrectly (off by 1). Add a comma after the "#CP" entry to resolve this issue. Fixes: 5277540e37e88a1a69f9517c4ad895051b4b3ed3 Cc: Allen Wynn <Allen_Wynn@Dell.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <40e55bf6563ed8ea4962a1219efbe1ab77a56cc4.1620919615.git.thomas.lendacky@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/VirtioFsDxe: suppress incorrect gcc warningsSergei Dmitrouk2021-05-141-0/+11
| | | | | | | | | | | | | | | `CreateDirectoryIfCreating` is used only if `PermitCreation` is set. `NewNodeIsDirectory` might not set in case of error, but that would lead to leaving the function before invalid use. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Message-Id: <20210511225616.5942-3-sergei@posteo.net> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ShellPkg/UefiShellCommandLib: suppress incorrect gcc warningSergei Dmitrouk2021-05-141-0/+5
| | | | | | | | | | | | | `Dupes` is used only if `Duplicates != NULL` and function is left if allocation of memory for `Dupes` fails, so it can't be used uninitialized. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3228 Cc: Ray Ni <ray.ni@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Signed-off-by: Sergei Dmitrouk <sergei@posteo.net> Message-Id: <20210511225616.5942-2-sergei@posteo.net> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* CryptoPkg: BaseCryptLib: Add RSA PSS verify supportSachin Agrawal2021-05-1421-0/+970
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3314 This patch uses Openssl's EVP API's to perform RSASSA-PSS verification of a binary blob. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Xiaoyu Lu <xiaoyux.lu@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Signed-off-by: Sachin Agrawal <sachin.agrawal@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* BaseTools: Add support for version 3 of FMP Image Header structureSughosh Ganu2021-05-122-9/+24
| | | | | | | | | | | Add support for the ImageCapsuleSupport field, introduced in version 3 of the EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER structure. This structure member is used to indicate if the corresponding payload has support for authentication and dependency. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* UefiCpuPkg/MpInitLib: Properly cast from PCD to SEV-ES jump table pointerLendacky, Thomas2021-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3385 A VS2012 build fails with a cast conversion warning when the SEV-ES work area PCD is cast as a pointer to the SEV_ES_AP_JMP_FAR type. When casting from a PCD value to a pointer, the cast should first be done to a UINTN and then to the pointer. Update the code to perform a cast to a UINTN before casting to a pointer to the SEV_ES_AP_JMP_FAR type. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Fixes: 7b7508ad784d16a5208c8d12dff43aef6df0835b Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <c89bc819856d448360430c32cb3833a9667f987b.1620656694.git.thomas.lendacky@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* SecurityPkg: Add support for RngDxe on AARCH64Rebecca Cran2021-05-1111-175/+480
| | | | | | | | | | | | | AARCH64 support has been added to BaseRngLib via the optional ARMv8.5 FEAT_RNG. Refactor RngDxe to support AARCH64, note support for it in the VALID_ARCHITECTURES line of RngDxe.inf and enable it in SecurityPkg.dsc. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/BaseRngLib: Add support for ARMv8.5 RNG instructionsRebecca Cran2021-05-1113-55/+602
| | | | | | | | | | Make BaseRngLib more generic by moving x86-specific functionality into 'Rand' and adding files under 'AArch64' to support the optional ARMv8.5 RNG instruction RNDR that is a part of FEAT_RNG. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* BaseTools: Fix DSC override of Guided toolMichael D Kinney2021-05-103-97/+190
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359 If the DSC file provides an override of a Guided tool path and/or Guided tool GUID value, then make sure the one from the DSC file is used if it is higher priority than the Guided tool in the tools_def.txt file. This makes the Guided tool used by GenFds match the tool listed GuidedSectionTools.txt. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* ArmPkg: Update SCMI Base Protocol version to 0x20000Nicola Mazzucato2021-05-102-9/+11
| | | | | | | | | | | | | The SCP-firmware has moved to full support for SCMIv2 which means that the base protocol can be either compliant with SCMI v1 or v2. Allow any version between SCMI v1.0 and SCMI v2.0 to be compatible with the current implementation. Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Tested-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* UnitTestFrameworkPkg: Sample unit test hangs when running in OVMF/QEMUGetnat Ejigu2021-05-044-0/+4
| | | | | | | | | | | | | Sample unit tests in UnitTestFrameworkPkg hangs when running in OVMF/QEMU environment. Build target is X64/GCC5. Fixing this issue by adding EFIAPI to ReportPrint() function that use VA_ARGS. Signed-off-by: Getnat Ejigu <getnatejigu@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* BaseTools: Fix New Target/ToolChain/Arch in DSC [BuildOptions] issuesMichael D Kinney2021-05-033-30/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359 * Save/Restore global state in GetToolChainAndFamilyFromDsc() This resolves an issue where the multi-arch build for UefiPayloadPkg would skip the autogen and build of IA32 components. * Expand tools wildcard. This resolves the issue where autogen makefile contents would have a BUIDLRULEFAMILY tools definitions with an '*' in the tool field that breaks the build from invalid makefile syntax. * Build rule family higher priority than Family. This resolves the issue where flags were appended from both the BUILDRULEFAMILY and FAMILY when only BUILDRULEFAMILY should be appended when present. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Steven Shi <steven.shi@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Andrew Fish <afish@apple.com>
* OvmfPkg/Tcg2ConfigPei: Update Depex for IA32 and X64Lendacky, Thomas2021-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345 The OVMF Tcg2Config PEIM adds the gOvmfTpmMmioAccessiblePpiGuid as a Depex for IA32 and X64 builds so that the MMIO range is properly mapped as unencrypted for an SEV-ES guest before the Tcg2Config PEIM is loaded. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <d6538e6c557173d260e272a0e5659683175e2e06.1619716333.git.thomas.lendacky@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/TpmMmioSevDecryptPei: Mark TPM MMIO range as unencrypted for SEV-ESLendacky, Thomas2021-04-3010-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345 During PEI, the MMIO range for the TPM is marked as encrypted when running as an SEV guest. While this isn't an issue for an SEV guest because of the way the nested page fault is handled, it does result in an SEV-ES guest terminating because of a mitigation check in the #VC handler to prevent MMIO to an encrypted address. For an SEV-ES guest, this range must be marked as unencrypted. Create a new x86 PEIM for TPM support that will map the TPM MMIO range as unencrypted when SEV-ES is active. The gOvmfTpmMmioAccessiblePpiGuid PPI will be unconditionally installed before exiting. The PEIM will exit with the EFI_ABORTED status so that the PEIM does not stay resident. This new PEIM will depend on the installation of the permanent PEI RAM, by PlatformPei, so that in case page table splitting is required during the clearing of the encryption bit, the new page table(s) will be allocated from permanent PEI RAM. Update all OVMF Ia32 and X64 build packages to include this new PEIM. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <42794cec1f9d5bc24cbfb9dcdbe5e281ef259ef5.1619716333.git.thomas.lendacky@amd.com> [lersek@redhat.com: refresh subject line] Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: Define a new PPI GUID to signal TPM MMIO accessabilityLendacky, Thomas2021-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | Define a new PPI GUID that is to be used as a signal of when it is safe to access the TPM MMIO range. This is needed so that, when SEV is active, the MMIO range can be mapped unencrypted before it is accessed. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Cc: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <03e292339273721724c8b14605cfe9d7bbe45a71.1619716333.git.thomas.lendacky@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/VmgExitLib: Add support for new MMIO MOV opcodesLendacky, Thomas2021-04-301-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345 Enabling TPM support results in guest termination of an SEV-ES guest because it uses MMIO opcodes that are not currently supported. Add support for the new MMIO opcodes (0xA0 - 0xA3), MOV instructions which use a memory offset directly encoded in the instruction. Also, add a DEBUG statement to identify an unsupported MMIO opcode being used. Fixes: c45f678a1ea2080344e125dc55b14e4b9f98483d Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <2fdde57707b52ae39c49341c9d97053aaff56e4a.1619716333.git.thomas.lendacky@amd.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* OvfmPkg/VmgExitLib: Properly decode MMIO MOVZX and MOVSX opcodesLendacky, Thomas2021-04-301-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3345 The MOVZX and MOVSX instructions use the ModRM byte in the instruction, but the instruction decoding support was not decoding it. This resulted in invalid decoding and failing of the MMIO operation. Also, when performing the zero-extend or sign-extend operation, the memory operation should be using the size, and not the size enumeration value. Add the ModRM byte decoding for the MOVZX and MOVSX opcodes and use the true data size to perform the extend operations. Additionally, add a DEBUG statement identifying the MMIO address being flagged as encrypted during the MMIO address validation. Fixes: c45f678a1ea2080344e125dc55b14e4b9f98483d Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <5949d54cb2c9ab69256f67ed5654b32654c0501c.1619716333.git.thomas.lendacky@amd.com>
* BaseTools/Source/Python: New Target/ToolChain/Arch in DSC [BuildOptions]Michael D Kinney2021-04-295-96/+230
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3359 Update BaseTools to support new build targets, new tool chains, and new architectures declared in DSC file [BuildOptions] sections. * Do not expand * when tools_def.txt is parsed. Only expand when both tools_def.txt and DSC [BuilsOptions] sections have been parsed. This also requires more flexible matching of tool keys that contain * in tool key fields. * Pre-scan the platform DSC file for FAMILY and TOOLCHAIN declarations DSC in [BuildOptions] sections before the FAMILY and TOOLCHAIN need to be known. Cc: Bob Feng <bob.c.feng@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Yuwei Chen <yuwei.chen@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
* EmulatorPkg: Temp remove IA32 GCC CI buildsMichael D Kinney2021-04-291-53/+0
| | | | | | | | | | | | | | | | | | | EmulatorPkg IA32 GCC builds are not working due to a failure to install the i386 library dependencies in Ubuntu 18.04. Temporarily disable these specific CI tests until the issue can be resolved. Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Bob Feng <bob.c.feng@intel.com> Cc: Yuwei Chen <yuwei.chen@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* AzurePipelines: Add support for ArmPlatformPkgPierre Gondois2021-04-281-2/+2
| | | | | | | | | | | | | | Add an entry to build the ArmPlatformPkg in the CI. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3349 Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* AzurePipelines: Add support for ArmPkgPierre Gondois2021-04-281-0/+3
| | | | | | | | | | | | | | Add an entry to build the ArmPkg in the CI. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=3348 Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* .pytool: Document LicenseCheck and EccCheckPierre Gondois2021-04-281-0/+10
| | | | | | | | | | | | | | Add an entry in the documentation for the LicenseCheck and EccCheck plugins. Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Acked-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 20:08:12 +0000