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* NetworkPkg: Dhcp6Dxe: SECURITY PATCH CVE-2023-45230 PatchDoug Flick via groups.io2024-02-064-239/+668
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4535 Bug Details: PixieFail Bug #2 CVE-2023-45230 CVSS 8.3 : CVSS:3.1/AV:A/AC:L/PR:N/UI:N/S:U/C:H/I:L/A:H CWE-119 Improper Restriction of Operations within the Bounds of a Memory Buffer Changes Overview: > -UINT8 * > +EFI_STATUS > Dhcp6AppendOption ( > - IN OUT UINT8 *Buf, > - IN UINT16 OptType, > - IN UINT16 OptLen, > - IN UINT8 *Data > + IN OUT EFI_DHCP6_PACKET *Packet, > + IN OUT UINT8 **PacketCursor, > + IN UINT16 OptType, > + IN UINT16 OptLen, > + IN UINT8 *Data > ); Dhcp6AppendOption() and variants can return errors now. All callsites are adapted accordingly. It gets passed in EFI_DHCP6_PACKET as additional parameter ... > + // > + // Verify the PacketCursor is within the packet > + // > + if ( (*PacketCursor < Packet->Dhcp6.Option) > + || (*PacketCursor >= Packet->Dhcp6.Option + (Packet->Size - sizeof (EFI_DHCP6_HEADER)))) > + { > + return EFI_INVALID_PARAMETER; > + } ... so it can look at Packet->Size when checking buffer space. Also to allow Packet->Length updates. Lots of checks added. Cc: Saloni Kasbekar <saloni.kasbekar@intel.com> Cc: Zachary Clark-williams <zachary.clark-williams@intel.com> Signed-off-by: Doug Flick [MSFT] <doug.edk2@gmail.com> Reviewed-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
* MdeModulePkg: Optimize CoreConnectSingleControllerZhi Jin2024-02-061-1/+6
| | | | | | | | | | | | CoreConnectSingleController() searches for the Driver Family Override Protocol drivers by looping and checking each Driver Binding Handles. This loop can be skipped by checking if any Driver Family Override Protocol installed in the platform first, to improve the performance. Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Zhi Jin <zhi.jin@intel.com>
* MdeModulePkg: Remove handle validation check in CoreGetProtocolInterfaceZhi Jin2024-02-061-6/+12
| | | | | | | | | | | | | | | | | | | | CoreGetProtocolInterface() is called by CoreOpenProtocol(), CoreCloseProtocol() and CoreOpenProtocolInformation(). Before CoreOpenProtocol() calls CoreGetProtocolInterface(), the input parameter UserHandle has been already checked for validation. So does CoreCloseProtocol(). Removing the handle validation check in CoreGetProtocolInterface() could improve the performance, as CoreOpenProtocol() is called very frequently. To ensure the assumption that the caller of CoreGetProtocolInterface() must pass in a valid UserHandle that is checked with CoreValidateHandle(), add the parameter check in CoreOpenProtocolInformation(), and declare CoreGetProtocolInterface() as static. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Zhi Jin <zhi.jin@intel.com>
* ArmVirtPkg: Move PlatformBootManagerLib to OvmfPkgChao Li2024-02-067-3/+2
| | | | | | | | | | | | | | | | | | | Moved the PlatformBootManagerLib to OvmfPkg and renamed to PlatformBootManagerLibLight for easy use by other ARCH. Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4663 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Lazlo Ersek <lersek@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg: Move two PCD variables into OvmfPkgChao Li2024-02-065-18/+17
| | | | | | | | | | | | | | | | | | Move the PcdTerminalTypeGuidBuffer and PcdUninstallMemAttrProtocol into OvmfPkg so other ARCH can easily use it. Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmVirtPkg: Move the FdtSerialPortAddressLib to OvmfPkgChao Li2024-02-066-3/+6
| | | | | | | | | | | | | | | | | | Move the FdtSerialPortAddressLib to Ovmfpkg so that other ARCH can easily use it. Build-tested only (with "ArmVirtQemu.dsc and OvmfPkgX64.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/RiscVVirt: Remove PciCpuIo2Dxe from RiscVVirtChao Li2024-02-062-605/+0
| | | | | | | | | | | CpuIo2Dxe is already used by RiscVVirt, so remove it. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/RiscVVirt: Enable CpuMmio2DxeChao Li2024-02-062-2/+2
| | | | | | | | | | | | | CpuMmio2Dxe is supports MMIO, enable it. Build-tested only (with "RiscVVirtQemu.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* ArmVirtPkg: Enable CpuMmio2DxeChao Li2024-02-067-7/+7
| | | | | | | | | | | | | | | | CpuMmio2Dxe is supports MMIO, enable it. Build-tested only (with "ArmVirtQemu.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Add a new CPU IO 2 driver named CpuMmio2DxeChao Li2024-02-064-0/+624
| | | | | | | | | | | | | | | | | | | | | | CpuIo2Dxe only supports IO to access to CPU IO. Some ARCHs that do not implement ports for CPU IO require MMIO to access PCI IO, and they pretty much put the IO devices under the LPC bus, which is usually under the PCIe/PCI bus. CpuMmio2Dxe was added to meet these needs. CpuMmio2Dxe depends on PcdPciIoTranslation. The code is copied from ArmPkg. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Ray Ni <ray.ni@intel.com>
* ArmVirtPkg: Move PCD of FDT base address and FDT padding to OvmfPkgChao Li2024-02-0616-33/+42
| | | | | | | | | | | | | | | | | | | | | Moved PcdDeviceTreeInitialBaseAddress and PcdDeviceTreeAllocationPadding to OvmfPkg for easier use by other architectures. Build-tested only (with "ArmVirtQemu.dsc"). BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* EmbeddedPkg: Add PcdPrePiCpuIoSize width for LOONGARCH64Chao Li2024-02-061-0/+3
| | | | | | | | | | | | | Added LoongArch64 architecture CPU IO width. https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Abner Chang <abner.chang@amd.com> Cc: Daniel Schaefer <git@danielschaefer.me> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg: Add some comments for LoongArch exceptionsChao Li2024-02-061-0/+14
| | | | | | | | | | | | Added some comments for registing LoongArch exceptions. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add a new library named PeiServicesTablePointerLibKs0Chao Li2024-02-065-4/+152
| | | | | | | | | | | | | | | | | | Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides setting and getting the PEI service table pointer through the CSR KS0 register. The idea of this library is derived from ArmPkg/Library/PeiServicesTablePointerLib/ BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add IOCSR operation for LoongArchChao Li2024-02-063-0/+233
| | | | | | | | | | | | | | | Add IoCsrRead8, IoCsrRead16, IoCsrRead32, IoCsrRead64, IoCsrWrite8, IoCsrWrite16, IoCsrWrite32, IoCsrWrite64 to operate the IOCSR registers of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add CSR operation for LoongArchChao Li2024-02-064-0/+550
| | | | | | | | | | | | | | | Add CsrRead, CsrWrite and CsrXChg functions for LoongArch, and use them to operate the CSR register of LoongArch architecture. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add read stable counter operation for LoongArchChao Li2024-02-063-0/+37
| | | | | | | | | | | | | Add LoongArch gets stable counter ASM function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch Cpucfg functionChao Li2024-02-065-1/+606
| | | | | | | | | | | | | | | | Add LoongArch AsmCpucfg function and Cpucfg definitions. Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of EccCheck. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 local interrupt function set into BaseLibChao Li2024-02-063-10/+54
| | | | | | | | | | | | | | | Adding LoongArch local interrupt function set, which is used to control the opening or closing of the local interrupt when the global interrupt is enabled. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 exception function set into BaseLibChao Li2024-02-063-0/+62
| | | | | | | | | | | | | | Adding SetExceptionBaseAddress and SetTlbRebaseAddress functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add LoongArch64 FPU function set into BaseCpuLibChao Li2024-02-065-7/+128
| | | | | | | | | | | | | | Adding InitializeFloatingPointUnits, EnableFloatingPointUnits and DisableFloatingPointUnits functions for LoongArch64. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add the header file named Csr.h for LoongArch64Chao Li2024-02-061-0/+263
| | | | | | | | | | | | | Adding Csr.h for LoongArch64, it is use for accessing the CSR registers. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiCpuPkg/PiSmmCpuDxeSmm:Map SMRAM in 4K page granularityDun Tan2024-02-061-24/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to map SMRAM in 4K page granularity during SMM page table initialization(SmmInitPageTable) so as to avoid the SMRAM paging-structure layout change when SMI happens (PerformRemainingTasks). The reason is to avoid the Paging-Structure change impact to the multiple Processors. Refer SDM section "4.10.4" & "4.10.5". Currently, SMM BSP needs to update the SMRAM range paging attribute in smm page table according to the SmmMemoryAttributesTable when SMM ready to lock happens. If the SMRAM range is not 4k mapped in page table, the page table update process may split 1G/2M paging entries to 4k ones.Meanwhile, all APs are still running in SMI, which might access the affected linear-address range between the time of modification and the time of invalidation access. That will be a potential problem leading exception happens. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Add more Paging mode enumerationDun Tan2024-02-061-1/+7
| | | | | | | | | | | | | Add more Paging mode enumeration in CpuPageTableLib to support forced mapping a range in 4K page granularity. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Reduce and optimize access to attributeZhou Jianfeng2024-02-061-33/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is to reduce and optimize access to attribute in CpuPageTableLib. Unreasonable writing to attribute of page table may leads to expection. The assembly code for C code Pnle->Bits.Present = Attribute->Bits.Present looks like: and dword [rcx], 0xfffffffe and eax, 0x1 or [rcx], eax In case Pnle->Bits.Present and Attribute->Bits.Present is 1, Pnle->Bits.Present will be set to 0 for short time(2 instructions) which is unexpected. If some other core is accessing the page, it may leads to expection. This change reduce and optimize access to attribute of page table, attribute of page table is set only when it need to be changed. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* BaseTools/Scripts/PatchCheck.py: Check for Change-idPierreGondois2024-02-041-1/+17
| | | | | | | | | | | | | | | | Code review tools like gerrit might use a 'Change-id' tag to track the evolution of patches. This tag should be removed before submitting a patch to the mailing-list. It has been observed that contributors sometimes forget to remove this tag. Add a check in PatchCheck.py to automate this. Also add a '--ignore-change-id' command line parameter to ignore the above check. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Yuwei Chen <yuwei.chen@intel.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
* UefiCpuPkg: Add cache operations support for Arch protoDhaval Sharma2024-02-042-0/+15
| | | | | | | | | | | | | | With CMO operations available for RISC-V, utilize them in CPU Architecture protocol. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sunil VL <sunilvl@ventanamicro.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/ResetVector: Fix SNP CPUID table processing results for ECX/EDXTom Lendacky2024-02-031-2/+2
| | | | | | | | | | | | | | The current support within the boot SNP CPUID table processing mistakenly swaps the ECX and EDX results. It does not have an effect at this time because current CPUID results checking does not check ECX or EDX. However, any future CPUID checks that need to check ECX or EDX may have erroneous behavior. Fix the assembler code to save ECX and EDX to the proper locations. Fixes: 34819f2caccb ("OvmfPkg/ResetVector: use SEV-SNP-validated CPUID values") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Michael Roth <michael.roth@amd.com>
* StandaloneMmPkg/Core: Output status in MMI handler assertionMichael Kubacki2024-02-031-1/+1
| | | | | | | | | | Currently, if a MMI handler returns an unexpected failure status code, ASSERT (FALSE) is used. It is more useful to use ASSERT_EFI_ERROR() which also outputs the status code value. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* ShellPkg: Update smbiosview for LoongArchDongyan Qian2024-02-022-0/+76
| | | | | | | | | | | According to SMBIOS spec3.6, LoongArch information support has been added, so this patch is submitted for display as information in smbiosview. Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg: Dxe: add LOONGARCH64 to mMachineTypeInfoDongyan Qian2024-02-021-6/+7
| | | | | | | | | | | This fixes messages like: "Image type X64 can't be loaded on <Unknown> UEFI system" Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Reviewed-by: Chao Li <lichao@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* UefiPayloadPkg/Crypto: Support external Crypto drivers.MarsX Lin2024-02-011-0/+2
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4661 There is potential build problem when CRYPTO_PROTOCOL_SUPPORT is set to TRUE and CRYPTO_DRIVER_EXTERNAL_SUPPORT is set to TRUE Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* OvmfPkg/IoMmuDxe: Provide an implementation for SetAttributeTom Lendacky2024-01-311-2/+53
| | | | | | | | | | | | | | | | | A recent change to the PciIoMap() function now propagates the return code from the IoMmu protocol SetAttribute() operation. The implementation of this operation in OvmfPkg/IoMmuDxe/CcIoMmu.c returns EFI_UNSUPPORTED, resulting in a failure to boot the guest. Provide an implementation for SetAttribute() that validates the IoMmu access method being requested against the IoMmu mapping operation. Suggested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <c0f9e95f557b601a045da015c1a97201e8aec2ab.1706634932.git.thomas.lendacky@amd.com> Tested-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topologyAbdul Lateef Attar2024-01-312-2/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AMD's new extended topology. If processor supports CPUID 80000026 leaf then obtain the topology information using new method. Algorithm: if CPUID is AMD: then check for AMD's extended cpu tology leaf. if yes then extract cpu tology based on AMD programmer manual's instruction. else then fallback to existing topology function. endif endif Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Message-Id: <d93822d37fd25dafd32795758cf47263b432e102.1705549445.git.AbdulLateef.Attar@amd.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
* MdePkg: Adds AMD Extended CPU topology CPUIDAbdul Lateef Attar2024-01-311-1/+22
| | | | | | | | | | | | | | | | Adds cpuid macro for AMD extended CPU topology. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Message-Id: <15199aaefbc497bb1ea7b20028c13ebedd8c488b.1705549445.git.AbdulLateef.Attar@amd.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
* Basetools: Include PCD declarations from Library Instancelevi.yun2024-01-311-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch "[PATCH v3 1/2] StandaloneMmPkg: Make StandaloneMmCpu driver architecture independent" (https://edk2.groups.io/g/devel/message/109178) removed ArmPkg/ArmPkg.dec from the Packages section in the INF file: StandaloneMmPkg/Drivers/StandaloneMmCpu/StandaloneMmCpu.inf This change was done as part of making the StandaloneMmCpu driver architecture independent. Although this change is correct, it results in a side effect here some platforms that utilise PCDs declared in ArmPkg.dec are no longer declared. An example of this issue can be seen when building edk2-platforms/Platform/ARM/SgiPkg/PlatformStandaloneMm.dsc $ build -a AARCH64 -t GCC -p Platform/ARM/SgiPkg/PlatformStandaloneMm.dsc build.py... /mnt/source/edk2-platforms/Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf(23): error F001: PCD (gArmTokenSpaceGuid.PcdFdBaseAddress) used in FDF is not declared in DEC files. As seen above, removing ArmPkg.dec from the Packages section in the StandAloneMmCpu Driver Inf file triggers build failure. Although, ArmPkg.dec is included in other Library Instances, the build system does not include the declarations from .dec files defined in Library instances. The build system only includes the PCD declarations from DEC files that are specified in INF files for Modules (components). Therefore, extend the build system to include the Packages from Library Instances so that the PCD declarations from the respective package DEC files are included. This patch can be seen on https://github.com/LeviYeoReum/edk2/tree/levi/2848_dec_check_on_library Signed-off-by: levi.yun <yeoreum.yun@arm.com> Tested-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* MdeModulePkg/Core/Dxe: Set MemoryTypeInfo bin range from HOBMichael D Kinney2024-01-304-8/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an optional method for PEI to declare a specific address range to use for the Memory Type Information bins. The current algorithm uses heuristics that tends to place the Memory Type Information bins in the same location, but memory configuration changes across boots or algorithm changes across a firmware updates could potentially change the Memory Type Information bin location. If the bin locations move across an S4 save/resume cycle, then the S4 resume may fail. Enabling this feature increases the number of scenarios that an S4 resume operation may succeed. If the HOB List contains a Resource Descriptor HOB that describes tested system memory and has an Owner GUID of gEfiMemoryTypeInformationGuid, then use the address range described by the Resource Descriptor HOB as the preferred location of the Memory Type Information bins. If this HOB is not detected, then the current behavior is preserved. The HOB with an Owner GUID of gEfiMemoryTypeInformationGuid is ignored for the following conditions: * The HOB with an Owner GUID of gEfiMemoryTypeInformationGuid is smaller than the Memory Type Information bins. * The HOB list contains more than one Resource Descriptor HOB with an owner GUID of gEfiMemoryTypeInformationGuid. * The Resource Descriptor HOB with an Owner GUID of gEfiMemoryTypeInformationGuid is the same Resource Descriptor HOB that that describes the PHIT memory range. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Aaron Li <aaron.li@intel.com> Cc: Liu Yun <yun.y.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/Core/Dxe: Initialize GCD before RT memory allocationsMichael D Kinney2024-01-302-16/+20
| | | | | | | | | | | | | | | | | Update the DxeMain initialization order to initialize GCD services before any runtime allocations are performed. This is required to prevent runtime data fragmentation when the UEFI System Table and UEFI Runtime Service Table are allocated before both the memory and GCD services are initialized. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Aaron Li <aaron.li@intel.com> Cc: Liu Yun <yun.y.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg: Disable watchdog interaction after exiting boot servicesRebecca Cran2024-01-301-4/+17
| | | | | | | | | Update GenericWatchdogDxe to disable watchdog interaction after exiting boot services. Also, move the mEfiExitBootServicesEvent event to the top of the file with the other static variables. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Introduce global mTimerPeriod and remove calculationRebecca Cran2024-01-301-18/+14
| | | | | | | | | | The calculation of the timer period was broken. Introduce a global mTimerPeriod so the calculation can be removed. Since mTimerFrequencyHz is only used in one place, remove the global and make it a local variable. Do the same with mNumTimerTicks. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Update GenericWatchdogDxe to allow setting full 48-bit offsetRebecca Cran2024-01-302-7/+52
| | | | | | | | | | | | The generic watchdog offset register is 48 bits wide, and can be set by performing two 32-bit writes. Add support for writing the high 16 bits of the offset register and update the signature of the WatchdogWriteOffsetRegister function to take a UINT64 value. Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* OvmfPkg/ResetVector: send post codes to qemu debug consoleGerd Hoffmann2024-01-292-0/+40
| | | | | | | | | | | | Neat when doing ResetVector coding. Incompatible with TDX and SEV, therefore not enabled by default. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Erdem Aktas <erdemaktas@google.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240129122929.349726-1-kraxel@redhat.com> [lersek@redhat.com: replace "SEV" with "SEV-ES/SEV-SNP" in comment]
* PcAtChipsetPkg/HpetTimerDxe: Fix nested interrupt time accuracyMichael D Kinney2024-01-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4659 When HPET timer is used as the timer interrupt and nested interrupts into the HPET timer interrupt handler occur, the elapsed time passed into the DXE Core is sometime too large and this causes the DXE Core internal system time to run too fast. Fix the logic so the previous main counter value stored in the module global variable mPreviousMainCounter is always captured before the timer notification function is called. Without this change, mPreviousMainCounter is updated after the timer notification function is called and when nesting occurs, it updates with the value from the first level of nesting which is further back in time than the interrupt from the deepest level of nesting. This causes the next two timer interrupts to compute a TimerPeriod that is twice the actual time period since the last interrupt and this causes the DXE Core internal time to run faster than expected. Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* DynamicTablesPkg: Exempt some _CPC field from checksPierre Gondois2024-01-292-4/+27
| | | | | | | | | | | | | | | | | | | | | When generating _CPC objects, some fields are mandatory by spec [1]. Some fields cannot be supported by a the Juno platform, which is used to test the _CPC generation. Therefore, rely on the PcdDevelopmentPlatformRelaxations Pcd to either: - warn about the missing fields and and let the OS handle the missing information - consider the missing fields as an error _CPC fields that are exempted from checks when the Pcd is set: - PerformanceLimitedRegister - ReferencePerformanceCounterRegister - DeliveredPerformanceCounterRegister [1] Cf. non-optional fields in: ACPI 6.5, s8.4.6.1 '_CPC (Continuous Performance Control)' Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add PcdDevelopmentPlatformRelaxations PcdPierre Gondois2024-01-291-0/+4
| | | | | | | | | | | | Some development platforms might not be compliant on some points of some specifications. In order to have a generic code accurately checking against specifications while still allowing some relaxation on specific points for the platforms that desire it, add a Pcd acting as a bitfield to warn instead of returning an error in case of non-compliance. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add DynamicTablesScmiInfoLibPierre Gondois2024-01-296-0/+371
| | | | | | | | | | | | | The SCP holds some power information that could be advertised through the _CPC object. The communication with the SCP is done through SCMI protocols (c.f. ArmScmiDxe). Use the SCMI protocols to query information and feed it to the DynamicTablesPkg. Acked-by: Leif Lindholm <quic_llindhol@quicinc.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Generate _PSD in SsdtCpuTopologyGeneratorPierre Gondois2024-01-291-0/+96
| | | | | | | | | | | | Make use of the newly added AmlCreatePsdNode() to generate _PSD objects. _PSD objects allow to describe 'performance control, P-state or CPPC, logical processor dependency', Cf. ACPI 6.4, s8.4.5.5 _PSD (P-State Dependency). Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* DynamicTablesPkg: Add AmlCreatePsdNode() to generate _PSDPierre Gondois2024-01-292-2/+221
| | | | | | | | | | Add AmlCreatePsdNode() to the AmlLib to generate _PSD objects. _PSD objects allow to describe 'performance control, P-state or CPPC, logical processor dependency', Cf. ACPI 6.5, s8.4.5.5 _PSD (P-State Dependency). Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* DynamicTablesPkg: Add PsdToken field to CM_ARM_GICC_INFO objectPierre Gondois2024-01-292-1/+7
| | | | | | | | | | The _PSD object (cf. ACPI 6.5, s8.4.5.5 _PSD (P-State Dependency) allows to describe CPU's power state dependencies. Add a PsdToken field to the CM_ARM_GICC_INFO object so that interdependent CPUs can reference the same CM_ARM_PSD_INFO object. Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
* DynamicTablesPkg: Add CM_ARM_PSD_INFO objectPierre Gondois2024-01-293-0/+41
| | | | | | | | | Add an object describing _PSD information, cf. ACPI 6.5, s8.4.5.5 _PSD (P-State Dependency). Also add the corresponding CmObjParser. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 22:09:53 +0000