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* ArmPkg: add reenable hook to ArmGenericTimerCounterLibArd Biesheuvel2018-04-261-0/+1
| | | | | | | | | | | | | | In preparation of selectively reinstating the timer enable quirk for Xen that we removed in commit 411a373ed642 ("ArmPkg/TimerDxe: remove workaround for KVM timer handling"), add a ArmGenericTimerReenableTimer() library function to ArmGenericTimerCounterLib that we will populate for Xen only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Julien Grall <julien.grall@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
* ArmPkg: Introduce SCMI protocolGirish Pathak2018-04-2311-0/+2046
| | | | | | | | | | | | | | | | | | | This change introduces a new SCMI protocol driver for Arm systems. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure various clocks available on the platform e.g. HDLCD clock on the Juno platforms. Whereas performance management protocol allows adjustment of various performance domains. Currently this is used to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/TimerDxe: remove workaround for KVM timer handlingArd Biesheuvel2018-04-191-1/+0
| | | | | | | | | | | | | | | | When we first ported EDK2 to KVM/arm, we implemented a workaround for the quirky timer handling on the KVM side. This has been fixed in Linux commit f120cd6533d2 ("KVM: arm/arm64: timer: Allow the timer to control the active state") dated 23 June 2014, which was incorporated into Linux release 4.3. So almost 4 years later, it should be safe to drop this workaround on the EDK2 side. This reverts commit b1a633434ddc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/CpuDxe: order CpuDxe after ArmGicDxe via protocol depexLaszlo Ersek2018-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Commit 61a7b0ec634f ("ArmPkg/Gic: force GIC driver to run before CPU arch protocol driver", 2018-02-06) explains why CpuDxe should be dispatched after ArmGicDxe. To implement the ordering, we should use a regular protocol depex rather than the less flexible AFTER opcode. ArmGicDxe installs gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid as one of the last actions on its entry point stack; either of those is OK for CpuDxe to wait for. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: annotate protocol usage in "ArmGicDxe.inf"Laszlo Ersek2018-04-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | "ArmGicDxe.inf" currently does not document how the protocols in the [Protocols] section are used. Such comments help us analyze behavior, so let's add them now. - gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid are always produced on the InterruptDxeInitialize() -> (GicV2DxeInitialize() | GicV3DxeInitialize()) -> InstallAndRegisterInterruptService() call path. - gEfiCpuArchProtocolGuid is consumed in the CpuArchEventProtocolNotify() protocol notify callback. (Technically this is "conditional"; however the firmware cannot work without architectural protocols, so we can call it unconditional.) While at it, drop the gArmGicDxeFileGuid comment from FILE_GUID; we're going to make that GUID uninteresting soon. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/TimerDxe: Add ISB for timer compare value reloadHeyi Guo2018-03-151-0/+1
| | | | | | | | | | | | If timer interrupt is level sensitive, reloading timer compare register has a side effect of clearing GIC pending status, so a "ISB" is needed to make sure this instruction is executed before enabling CPU IRQ, or else we may get spurious timer interrupts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/TimerDxe: Always perform an EOI, even for spurious interruptsMarc Zyngier2018-03-061-6/+4
| | | | | | | | | | | | | | | | | | | The generic timer driver only EOIs the timer interrupt if the ISTATUS bit is set. This is completely fine if you pretend that spurious interrupts do not exist. But as a matter of fact, they do, and the first one will leave the interrupt activated at the GIC level, making sure that no other interrupt can make it anymore. Making sure that each interrupt Ack is paired with an EOI is the way to go. Oh, and enabling the interrupt each time it is taken is completely pointless. We entered this function for a good reason... Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/Gic: force GIC driver to run before CPU arch protocol driverArd Biesheuvel2018-02-064-25/+52
| | | | | | | | | | | | | | | | | | | | | | | Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com>
* ArmPkg: delete references to unused guids/Pcds from CpuDxeLeif Lindholm2018-02-062-3/+0
| | | | | | | | | | gEfiDebugSupportPeriodicCallbackProtocolGuid and PcdCpuDxeProduceDebugSupport are referred to from CpuDxe. Delete references from .inf and .h. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove unused ArmGicSecLib library implementationArd Biesheuvel2017-11-262-152/+0
| | | | | | | | | | | This module is not used anywhere under edk2 or edk2-platforms, so let's remove it. This removes the only dependency on ArmPlatformLib from ArmPkg. While at it, remove a mention of ArmPlatformPkg from a comment in the .dec file as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/GenericWatchdogDxe: Set Watchdog interrupt typeArd Biesheuvel2017-10-052-14/+21
| | | | | | | | | | | | Utilise the new HardwareInterrupt2 protocol to adjust the Edge/Level characteristics of the Watchdog interrupt. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocolArd Biesheuvel2017-10-055-1/+341
| | | | | | | | | | | | | | | | | | | | | | | | The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Tidy GIC code before changes.Evan Lloyd2017-10-056-157/+220
| | | | | | | | | | | | | | | | | | | This change is purely cosmetic, to tidy some code before change. Mods involve: Re-order #includes Reformat comments. Use ns consistently (always "100ns" not sometimes "100 nS") Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Rationalize GIC register address calculations Replace explicit test and assert with ASSERT_EFI_ERROR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add ArmCrashDumpDxe driverArd Biesheuvel2017-09-063-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | Even though RELEASE builds produce some diagnostics when a crash occurs, they can be rather unhelpful: Synchronous Exception at 0x0000000000000000 and sometimes, it would be useful to get a full register dump from a production machine without having to modify the firmware. This can be achieved very easily by incorporating a DEBUG build of ARM's DefaultExceptionHandlerLib into a DXE driver, and registering its DefaultExceptionHandler entry point as the synchronous exception handler, overriding the default one. If we then build this driver using the UefiDebugLibConOut DebugLib implementation, we end up with a module than can simply be loaded via the Shell on any system. Shell> load fs0:ArmCrashDumpDxe.efi As a bonus, the crash dump will also appear on the graphical display, not only on the serial port. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove ArmCpuLib header and implementationsArd Biesheuvel2017-04-0613-557/+0
| | | | | | | | Remove ArmCpuLib entirely. It is no longer used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/CpuDxe: handle implied attributes in EfiAttributeToArmAttributeArd Biesheuvel2017-03-081-3/+7
| | | | | | | | | | | | | | | | Some memory attributes are implied by the memory type, e.g., device memory is always mapped non-executable and cached memory should have the inner shareable attribute. In order to prevent unnecessary memory attribute updates of mappings created early on, make EfiAttributeToArmAttribute() return these implied attributes in the same way as ArmMmuLib does already. This avoids false positives when looking for differences between current and desired mapping attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: remove VirtualMask arg from ArmSetMemoryAttributesArd Biesheuvel2017-03-071-1/+1
| | | | | | | | | | | | | We no longer make use of the ArmMmuLib 'feature' to create aliased memory ranges with mismatched attributes, and in fact, it was only wired up in the ARM version to begin with. So remove the VirtualMask argument from ArmSetMemoryAttributes()'s prototype, and remove the dead code that referred to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: move ARM version of SetMemoryAttributes to ArmMmuLibArd Biesheuvel2017-03-073-424/+2
| | | | | | | | | | | | | | | ... where it belongs, since AARCH64 already keeps it there, and non DXE users of ArmMmuLib (such as DxeIpl, for the non-executable stack) may need its functionality as well. While at it, rename SetMemoryAttributes to ArmSetMemoryAttributes, and make any functions that are not exported STATIC. Also, replace an explicit gBS->AllocatePages() call [which is DXE specific] with MemoryAllocationLib::AllocatePages(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: honour RO/XP attributes in SetMemoryAttributes()Ard Biesheuvel2017-03-071-92/+86
| | | | | | | | | | | | | | Enable the use of strict memory permissions on ARM by processing the EFI_MEMORY_RO and EFI_MEMORY_XP rather than ignoring them. As before, calls to CpuArchProtocol::SetMemoryAttributes that only set RO/XP bits will preserve the cacheability attributes. Permissions attributes are not preserved when setting the memory type only: the way the memory permission attributes are defined does not allows for that, and so this situation does not deviate from other architectures. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: avoid unnecessary cache/TLB maintenanceArd Biesheuvel2017-03-071-26/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Page and section entries in the page tables are updated using the helper ArmUpdateTranslationTableEntry(), which cleans the page table entry to the PoC, and invalidates the TLB entry covering the page described by the entry being updated. Since we may be updating section entries, we might be leaving stale TLB entries at this point (for all pages in the section except the first one), which will be invalidated wholesale at the end of SetMemoryAttributes(). At that point, all caches are cleaned *and* invalidated as well. This cache maintenance is costly and unnecessary. The TLB maintenance is only necessary if we updated any section entries, since any page by page entries that have been updated will have been invalidated individually by ArmUpdateTranslationTableEntry(). So drop the clean/invalidate of the caches, and only perform the full TLB flush if UpdateSectionEntries() was called, or if sections were split by UpdatePageEntries(). Finally, make the cache maintenance on the remapped regions themselves conditional on whether any memory type attributes were modified. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe ARM: avoid splitting page table sections unnecessarilyArd Biesheuvel2017-03-071-8/+43
| | | | | | | | | | | | | | | | | | Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is fully broken down into page mappings if the start or the size of the region happens to be misaliged relative to the section size of 1 MB. This is going to result in memory being wasted on second level page tables when we enable strict memory permissions, given that we remap the entire RAM space non-executable (modulo the code bits) when the CpuArchProtocol is installed. So refactor the code to iterate over the range in a way that ensures that all naturally aligned section sized subregions are not broken up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig()Ard Biesheuvel2017-02-283-0/+8
| | | | | | | | | | | | | | | To prevent the initial MMU->GCD memory space map synchronization from stripping permissions attributes [which we cannot use in the GCD memory space map, unfortunately], implement the same approach as x86, and ignore SetMemoryAttributes() calls during the time SyncCacheConfig() is in progress. This is a horrible hack, but is currently the only way we can implement strict permissions on arbitrary memory regions [as opposed to PE/COFF text/data sections only] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: remove VirtualUncachedPages protocol and implementationArd Biesheuvel2017-02-234-75/+0
| | | | | | | | | | Virtual uncached pages are simply pages that are aliased using mismatched attributes, which is not allowed by the ARM architecture. So remove the protocol and its implementation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissionsArd Biesheuvel2017-02-211-8/+0
| | | | | | | | | | | | | | Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissionsArd Biesheuvel2017-02-211-0/+7
| | | | | | | | | | | Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttributeArd Biesheuvel2017-02-212-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_MASK (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usageJiewen Yao2017-02-213-11/+11
| | | | | | | | | | | Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/GenericWatchdogDxe: Declare MMIO PCDs as UINT64Alexei2017-02-071-5/+5
| | | | | | | | | | | | | | PcdGenericWatchdogControlBase & PcdGenericWatchdogRefreshBase are declared as UINT32 values in ArmPkg.dec, but for platforms with addresses in the memory range above 4GB this causes build error F000: Too large PCD value for datum type [UINT32] of PCD gArmTokenSpaceGuid.PcdGenericWatchdogControlBase Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=361 Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel2017-01-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg/CpuDxe: set DmaBufferAlignment according to CWGArd Biesheuvel2016-11-021-1/+12
| | | | | | | | | | The DmaBufferAlignment currently defaults to 4, which is dangerously small and may result in lost data on platforms that perform non-coherent DMA. So instead, take the CWG value from the cache info registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmCortexA9Lib RVCT: remove incompatible GCC includeArd Biesheuvel2016-10-281-4/+0
| | | | | | | | | | Drop the include of AsmMacroIoLib.h, which contains GCC preprocessor macros that RVCT does not use or require, given it has its own AsmMacroIoLib.inc Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: Fix MMU initialization problemKurt Kennett2016-09-261-0/+5
| | | | | | | | | | | | | During Mmu initialization in the CpuDxe, for a page table any bits set in the 'NextSectionAttributes' are garbage and were set from bits that are actually part of the pagetable address. We clear it out to zero so that the SyncCacheConfigPage will use the page attributes instead of trying to convert the (bogus) section attributes into page attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Kurt Kennett <kurt.kennett@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicLib: use correct loop variableArd Biesheuvel2016-09-091-1/+1
| | | | | | | | | | | The ArmGicLib API function GicGetCpuRedistributorBase () declares GicCpuRedistributorBase to iterate over the redistributors of all CPUs, but then inadvertently advances GicRedistributorBase instead. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2016-09-082-4/+4
| | | | | | | | | | | According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-40/+16
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmCpuLib: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-112-15/+3
| | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: Fix double GIC EIOR write per interruptAlexei Fedorov2016-08-082-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug in the GIC v2 and v3 drivers where the GICC_EOIR (End Of Interrupt Register) is written twice for a single interrupt. GicV(2|3)IrqInterruptHandler() calls the Interrupt Handler and then GicV(2|3)EndOfInterrupt() on exit: InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt]; if (InterruptHandler != NULL) { // Call the registered interrupt handler. InterruptHandler (GicInterrupt, SystemContext); } else { DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt)); } GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt); although gInterrupt->EndOfInterrupt() can be expected to have already been called by InterruptHandler() [which is the case for the primary in-tree handler in TimerDxe] The fix moves the EndOfInterrupt() call inside the else case for unregistered/spurious interrupts. This removes a potential race condition that might have lost interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributorArd Biesheuvel2016-07-131-3/+22
| | | | | | | | | | | | Unlike SGIs and PPIs, which are private to the CPU and are managed at the redistributor level (which is also a per-CPU construct), shared interrupts (SPIs) are shared between all CPUs, and therefore managed at the distributor level (just as on GICv2). Reported-by: Narinder Dhillon <ndhillonv2@gmail.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Fix typos in commentsGiri P Mudusuru2016-07-111-1/+1
| | | | | | | | | | EFI_UNSUPPORTEDT to EFI_UNSUPPORTED Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel2016-07-071-0/+1
| | | | | | | | | | | | Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ArmPkg/CpuDxe: unmask SErrors in DEBUG buildsArd Biesheuvel2016-07-011-0/+9
| | | | | | | | | | | | | | | | | | | SErrors (formerly called asynchronous aborts) are a distinct class of exceptions that are not closely tied to the currently executing instruction. Since execution may be able to proceed in such a condition, this class of exception is masked by default, and software needs to unmask it explicitly if it is prepared to handle such exceptions. On DEBUG builds, we are well equipped to report the CPU context to the user and it makes sense to report an SError as soon as it occurs rather than to wait for the OS to take it when it unmasks them, especially since the current arm64/Linux implementation simply panics in that case. So unmask them when ArmCpuDxe loads. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel2016-06-231-0/+16
| | | | | | | | | | | | Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: implement CpuIo2 protocol driver specific for PCIArd Biesheuvel2016-04-292-0/+612
| | | | | | | | | | | | | | | | | The CpuIo2 protocol is required by the generic PciHostBridgeDxe driver, which relies on it to back its own I/O and MMIO operations. Since ARM has no native I/O port equivalent, such accesses can only originate from PCI drivers, and the PCI I/O space is translated to MMIO in this case. So we can implement this protocol using MMIO operations only, and take the PCI I/O translation offset into account when performing I/O port accesses. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Gic: Fix boundary checking bugHeyi Guo2016-04-253-9/+9
| | | | | | | | | mGicNumInterrupts is the total number of interrupts, so the interrupt ID equal to mGicNumInterrupts is also invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: apply Cortex-A57 errataLeendert van Doorn2016-03-251-3/+6
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: update CpuDxe to use CpuExceptionHandlerLibCohen, Eugene2016-03-177-1402/+98
| | | | | | | | | | Use the new ARM/AArch64 implementation of the base CpuExceptionHandlerLib library from CpuDxe to centralize exception handling. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: CpuDxe: don't track interrupt state in a global variableCohen, Eugene2016-02-231-5/+1
| | | | | | | | | | | Update the CpuDxe driver to remove an assumption that it is the only component modifying interrupt state since this can be done through BaseLib as well. Instead of using a global variable for last interrupt state we now check the current PSTATE value directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Rectify file modesEvan Lloyd2016-01-302-0/+0
| | | | | | | | | | | | | | | Problems have been encountered because some of the source files have execute permission set. This can cause git to report them as changed when they are checked out onto a file system with inherited permissions. This has been seen using Cygwin, MinGW and PowerShell Git. This patch makes no change to source file content, and only aims to correct the file modes/permissions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: use unified asm syntax for CLANGArd Biesheuvel2015-12-151-4/+5
| | | | | | | | | | | | | | | The CLANG assembler does not support the legacy, non-unified assembler syntax, i.e., it does not support the reordering of the condition suffixes with the increment/decrement before/after or byte/word suffixes, and it does not recognize the 'empty descending' (ED) suffix at all. So move to the unified syntax, and replace 'empty descending' with 'decrement after' or 'increment before' as appropriate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19280 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: fix bug in GICv3 distributor configurationArd Biesheuvel2015-12-151-2/+2
| | | | | | | | | | | | | | In the function ArmGicEnableDistributor (), the Affinity Routing Enable (ARE) bit, which essentially defines whether the GIC runs in v2 or v3 mode, is inadvertently cleared when enabling the GIC distributor if it is running in v3 mode. So fix that. Reported-by: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19274 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 00:11:18 +0000