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* ArmPkg/Include: Add ArmSvcLib header file.Supreeth Venkatesh2017-10-061-0/+46
| | | | | | | | | | ArmSvcLib header file to specify the SVC arguments structure and function prototype to trigger an SVC call. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add SVC function IDs for Management Mode.Supreeth Venkatesh2017-10-061-0/+43
| | | | | | | | | | | | | | SVCs are in the range 0xC4000060 - 0xC400007f. The functions available to the secure MM partition: 1. Signal completion of MM event handling. 2. Set/Get memory attributes for a memory region at runtime. 3. Get version number of secure partition manager. Also, it defines memory attributes required for set/get operations. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add standard SMC function IDs for MM interface.Supreeth Venkatesh2017-10-061-1/+19
| | | | | | | | | | | | | | | | | | | | This patch adds a list of function IDs that fall under the standard SMC range as defined in [1] SMCs associated with Management Mode are in the range 0xC4000040 - 0xC400005f (64 bit) and 0x84000040 - 0x8400005f (32 bit). The function(s) available to the normal world: 1. Request services from the secure MM environment using MM_COMMUNICATE. It also defines MM return codes. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocolArd Biesheuvel2017-10-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Tidy GIC code before changes.Evan Lloyd2017-10-051-16/+7
| | | | | | | | | | | | | | | | | | | This change is purely cosmetic, to tidy some code before change. Mods involve: Re-order #includes Reformat comments. Use ns consistently (always "100ns" not sometimes "100 nS") Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Rationalize GIC register address calculations Replace explicit test and assert with ASSERT_EFI_ERROR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove UncachedMemoryAllocationLibArd Biesheuvel2017-08-311-665/+0
| | | | | | | | | | | | | | Now that ArmDmaLib can take care of its own memory allocation needs, let's get rid of UncachedMemoryAllocationLib entirely. This forces platforms to declare the required semantics (non-cache coherent DMA, whichever way it is implemented), rather than using uncached memory allocations directly, which may not always be the right choice, and prevents sharing of drivers between platforms if one is cache coherent and the other is not. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Move IS_DEVICE_PATH_NODE for sharingJun Nie2017-08-011-0/+3
| | | | | | | | Move IS_DEVICE_PATH_NODE into header to share it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add CNTHCTL_EL2 support functionsSami Mujawar2017-05-221-1/+11
| | | | | | | | | | Added helper functions for reading and writing the CNTHCTL_EL2 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove ArmCpuLib header and implementationsArd Biesheuvel2017-04-061-28/+0
| | | | | | | | Remove ArmCpuLib entirely. It is no longer used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmMmuLib: remove VirtualMask arg from ArmSetMemoryAttributesArd Biesheuvel2017-03-071-2/+1
| | | | | | | | | | | | | We no longer make use of the ArmMmuLib 'feature' to create aliased memory ranges with mismatched attributes, and in fact, it was only wired up in the ARM version to begin with. So remove the VirtualMask argument from ArmSetMemoryAttributes()'s prototype, and remove the dead code that referred to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: move ARM version of SetMemoryAttributes to ArmMmuLibArd Biesheuvel2017-03-072-0/+14
| | | | | | | | | | | | | | | ... where it belongs, since AARCH64 already keeps it there, and non DXE users of ArmMmuLib (such as DxeIpl, for the non-executable stack) may need its functionality as well. While at it, rename SetMemoryAttributes to ArmSetMemoryAttributes, and make any functions that are not exported STATIC. Also, replace an explicit gBS->AllocatePages() call [which is DXE specific] with MemoryAllocationLib::AllocatePages(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: remove VirtualUncachedPages protocol and implementationArd Biesheuvel2017-02-231-60/+0
| | | | | | | | | | Virtual uncached pages are simply pages that are aliased using mismatched attributes, which is not allowed by the ARM architecture. So remove the protocol and its implementation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managedArd Biesheuvel2017-02-221-0/+12
| | | | | | | | | In preparation of enabling stack alignment checking, which is mandated by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissionsArd Biesheuvel2017-02-211-0/+4
| | | | | | | | | | | | | | Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel2017-01-205-196/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg: remove LoadConstantXxx() asm macrosArd Biesheuvel2016-10-283-73/+0
| | | | | | | | This is ancient cruft that is no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg RVCT: add ADRL/LDRL macro equivalentsArd Biesheuvel2016-10-281-0/+20
| | | | | | | | | | | | | | | The GCC ARM builds have access to ADRL/LDRL macros that emit relative symbol references, i.e., references that do not require fixing up at load time (or FV generation time for XIP modules) Implement equivalent functionality for RVCT: note that this does not use movw/movt pairs, but the more compatible add/add/add or add/add/ldr sequences (which Clang does not support, unfortunately, hence the use of movw/movt for the GCC toolchain family) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AsmMacroIoLib: force word alignment for functionsArd Biesheuvel2016-09-211-0/+1
| | | | | | | | | Without an explicit .align directive, the Clang assembler defaults to no alignment, which may result in instructions appearing misaligned in the final executable. So use word alignment in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: introduce ASM_FUNC, MOV32/MOV64 and ADRL/LDRL macrosArd Biesheuvel2016-08-112-1/+42
| | | | | | | | | | | | | | | | This introduces the ASM_FUNC() macro to annotate function entry points in assembler files. This allows us to add additional metadata that marks a function entry point as a function, and allows us to emit a .section directive for each function, which makes it possible for the linker to drop unreferenced code. In addition, introduce a couple of utility macros that we can use to clean up the code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AsmMacroIoLib: remove unused obsolete MMIO and other asm macrosArd Biesheuvel2016-08-112-267/+0
| | | | | | | | | | | | | | This removes the various Mmio ASM macros that are not used anywhere in the code, and removes some variants of LoadConstant... () that are not used anywhere either. Note that these MmioXxx() implementations are unrelated to the C versions defined in MdePkg. These are strictly intended for use in assembler, and no such uses remain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add Cortex-A72 CPU typeJeremy Linton2016-07-281-0/+1
| | | | | | | | Add the Cortex-A72 CPU type which is used in JunoR2. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: avoid type promotion in TCR_EL1 assignmentArd Biesheuvel2016-07-131-78/+62
| | | | | | | | | | | | | | | | | | | | | | Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1") introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30), and ORs it into the value to be written into TCR_EL1 (if executing at EL1). Since the constant is implicitly typed as signed int, and has the sign bit set, the promotion that occurs when casting to UINT64 results in a TCR value that has bits [63:32] all set, which includes mostly RES0 bits but also the TBIn, AS and IPS fields. So explicitly redefine all TCR related constants as 'unsigned long' types, using the UL suffix. To avoid confusion in the future, the inappropriately named VTCR_EL23_xxx constants have the leading V removed, and the actual VTCR_EL2 related constants are dropped, given that we never configure stage 2 translation in UEFI. Reported-by: Vishal Oliyil Kunnil <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel2016-07-071-38/+0
| | | | | | | | | | | | Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ArmPkg: introduce ArmMmuLib library classArd Biesheuvel2016-07-071-0/+65
| | | | | | | | | Introduce the library class ArmMmuLib, which encapsulates the functionality to set up and modify page table entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel2016-06-231-2/+3
| | | | | | | | | | | | Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: don't invalidate entire I-cache on range operationArd Biesheuvel2016-05-121-2/+8
| | | | | | | | | | | Instead of cleaning the data cache to the PoU by virtual address and subsequently invalidating the entire I-cache, invalidate only the range that we just cleaned. This way, we don't invalidate other cachelines unnecessarily. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AArch64Mmu: disable MMU during page table manipulationsArd Biesheuvel2016-04-141-0/+6
| | | | | | | | | | | | | | | | | | | | On ARM, manipulating live page tables is cumbersome since the architecture mandates the use of break-before-make, i.e., replacing a block entry with a table entry requires an intermediate step via an invalid entry, or TLB conflicts may occur. Since it is not generally feasible to decide in the page table manipulation routines whether such an invalid entry will result in those routines themselves to become unavailable, use a function that is callable with the MMU off (i.e., a leaf function that does not access the stack) to perform the change of a block entry into a table entry. Note that the opposite should never occur, i.e., table entries are never coalesced into block entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg/AsmMacroIoLibV8: remove undocumented assumption from ELx macrosArd Biesheuvel2016-03-221-8/+8
| | | | | | | | | | | | | | | The macros EL1_OR_EL2() and EL1_OR_EL2_OR_EL3() allow conditional execution of assembly sequences based on the current exception level, by jumping to caller supplied labels 1f, 2f or 3f. However, the jump to 1f is actually a fallthrough, which means the EL1 code needs to follow right after the macro invocation, and the 1f label is ignored. So let's fix this by making all jumps explicit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2016-03-161-0/+5
| | | | | | | | | Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Configure TTBCR registerEvan Lloyd2016-03-031-1/+7
| | | | | | | | | | | | | Architecturally, the TTBCR register value is undefined at reset for Non-Secure. On some platforms the reset value for TTBCR is not zero and this causes a data abort exception once the MMU is enabled. This patch configures the TTBCR register to enable translation table walk using TTBR0. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
* ArmPkg: rewrite vector table population macrosArd Biesheuvel2015-12-161-2/+5
| | | | | | | | | | | | | | | | | | | | | Unfortunately, Clang does not support the use of symbol references in .org directives, and bails with the following error message when it encounters them: <...>:error: expected assembly-time absolute expression .org DebugAgentVectorTable + 0x000 So replace the .org arguments with absolute values, and move the whole vector table into a subsection with the appropriate alignment, and starting at .org 0x0. This gives the same protection with respect to entries that exceed 128 bytes, in a way that Clang supports as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19303 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: update InvalidateInstructionCacheRange to flush only to PoUEugene Cohen2015-12-081-1/+7
| | | | | | | | | | | | | | | | | | | | This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to flush the data cache only to the point of unification (PoU). This improves performance and also allows invalidation in scenarios where it would be inappropriate to flush to the point of coherency (like when executing code from L2 configured as cache-as-ram). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Added AARCH64 and ARM/GCC implementations of the above. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg RVCT: add asm macro combining EXPORT, AREA and label definitionEugene Cohen2015-12-021-0/+29
| | | | | | | | | | | | | | In response to Leif's request earlier, this adds a new RVCT assembler macro to centralize the exporting of assembly functions including the EXPORT directive (so the linker can see it), the AREA directive (so it's in its own section for code size reasons) and the function label itself. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19098 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: remove SetPrimaryStack and InitializePrimaryStack macrosArd Biesheuvel2015-11-273-109/+0
| | | | | | | | | | | | The SetPrimaryStack and InitializePrimaryStack macros are no longer used now that we removed support for ArmPlatformGlobalVariableLib. So remove the various versions of them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19004 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () aliasLeif Lindholm2015-11-201-6/+0
| | | | | | | | | | | | | | | | | | In ArmLib, there exists an alias for ArmDataSynchronizationBarrier, named after one of several names for the pre-ARMv6 cp15 operation that was formalised into the Data Synchronization Barrier in ARMv6. This alias is also the one called from within ArmLib, in preference of the correct name. Through the power of code reuse, this name slipped into the AArch64 variant as well. Expunge it from the codebase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland2015-11-191-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: correct TTBR1_EL1 settings in TCR_EL1Mark Rutland2015-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since reset. Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU may make page table walks via TTBR1_EL1 at any time, potentially using UNKNOWN values. This can result in a number of potential problems (e.g. the CPU may load from MMIO registers as part of a page table walk). Additionally, in the presence of Cortex-A57 erratum #822227, we must program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a hypervisor which makes use of PAR_EL1. This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any CPU capable of running EDK2 must support this granule, and given TCR_EL1.EPD1, programming the field is not detrimental in the absence of the erratum. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBRArd Biesheuvel2015-11-181-4/+9
| | | | | | | | | | | | | Bits 0 and 6 of the TTBRx system registers have different meanings depending on whether a system implements the Multiprocessing Extensions. So use separate memory attribute definitions for MP and non-MP. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLEArd Biesheuvel2015-11-181-1/+1
| | | | | | | | | | | | The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not bit 0 set. Furthermore, the name is inconsistent with the other definitions so rename it to TTBR_INNER_NON_CACHEABLE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: make cached translation table accesses shareableArd Biesheuvel2015-11-181-3/+3
| | | | | | | | | | | To align with the way normal cacheable memory is mapped, set the shareable bit for cached accesses performed by the page table walker. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu: fix write-through translation table accessesArd Biesheuvel2015-11-181-1/+1
| | | | | | | | | | | | | | | | The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since a) its meaning is unclear in the context of TTBRx, since write through always implies Read-Allocate and no Write-Allocate b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC So instead, rename it to TTBR_WRITE_THROUGH and update the definition to reflect the name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Mmu: set required XN attributes for device mappingsArd Biesheuvel2015-11-181-0/+2
| | | | | | | | | | | | | | | | | | | To prevent speculative intruction fetches from MMIO ranges that may have side effects on reads, the architecture requires device mappings to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and EL1&0 translation regimes, respectively.) Note that, in the ARM case, this involves moving all accesses to a client domain since permission attributes like XN are ignored from a manager domain. The use of a client domain is actually mandated explicitly by the UEFI spec. Reported-by: Heyi Guo <heyi.guo@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()Ard Biesheuvel2015-11-181-5/+0
| | | | | | | | | | | | | The function GcdAttributeToArmAttribute() is not used anywhere in the code base, and is only defined for AARCH64 and not for ARM. It also fails to set the bits for shareability and non-executability that we require for correct operation. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18888 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: mark all cached mappings as (inner) shareableArd Biesheuvel2015-11-122-4/+9
| | | | | | | | | | | | | | | | | Mark all cached memory mappings as shareable (or inner shareable on AArch64) so that our view of memory is kept coherent by the hardware. This is relevant for things like coherent DMA and virtualization (where a guest may migrate to another core) but in general, since UEFI on ARM is mostly used in a context where the secure firmware and possibly a secure OS are already up and running, it is best to refrain from using any non-shareable mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: add accessor function for Cache Writeback GranuleArd Biesheuvel2015-11-091-0/+6
| | | | | | | | | | | | | Add a function to ArmLib that provides access to the Cache Writeback Granule (CWG) field in CTR_EL0. This information is required when performing non-coherent DMA. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18758 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove CCSIDR based cache info routinesArd Biesheuvel2015-11-091-78/+0
| | | | | | | | | | | | | | The ARM architecture does not allow the actual geometries of the caches to be inferred from the CCSIDR cache info system register, since the geometry it reports is intended for performing cache maintenance by set/way and nothing else. Since the ArmLib cache info routines are based solely on CCSIDR contents, they should not be used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18753 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove unused ArmCleanDataCacheToPoU()Ard Biesheuvel2015-11-091-6/+0
| | | | | | | | | | | | | | The function ArmCleanDataCacheToPoU() has no users, and its purpose is unclear, since it uses cache maintenance by set/way to perform the clean to PoU, which is a dubious practice to begin with. So remove the declaration and all definitions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18752 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg BeagleBoardPkg Omap35xxPkg: fix typo 'ArmDataSyncronizationBarrier'Ard Biesheuvel2015-11-091-1/+1
| | | | | | | | | | | | Replace all instances of ArmDataSyncronizationBarrier with ArmDataSynchronizationBarrier. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18751 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: remove unused ARM9 supportArd Biesheuvel2015-11-091-71/+0
| | | | | | | | | | | | The ARM9 ArmLib implementation is not referenced anywhere in the tree, and unlikely to be useful going forward, considering that ARM9 outdates even ARMv6. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18750 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Purge unused/unneeded CPU-specific header filesLeif Lindholm2015-11-063-173/+0
| | | | | | | | | | | | | | | | | | In ArmPkg/Include/Chipset, several CPU-specific header files reside. Most of these provide no actual, or very little, use. ARM1176JZ-S.h is not used at all (and unusable since SVN r18237). ArmAemV8.h simply includes AArch64.h. ArmCortexA15.h defines one processor-specific configuration bit and then includes ArmV7.h. Delete these include files, and update their sole users to function without them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18736 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-21 17:47:38 +0000