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* ArmPkg: Fix various typosAntoine Cœur2019-07-041-2/+2
| | | | | | | Fix various typos in ArmPkg. Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0933-231/+33
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidationArd Biesheuvel2019-01-291-1/+2
| | | | | | | | | | | | | | | | | | | Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: delete unused ArmTrustZoneSmc.hLeif Lindholm2019-01-211-161/+0
| | | | | | | | | | | | | ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h contains definitions contradicting the SMC Calling Convention (ARM DEN0028B). It also has no users in public trees. So delete before it can cause damage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ArmPkg/ArmScmiDxe: Add clock enable functionJeff Brasen2018-12-211-0/+197
| | | | | | | | | | | | | | | | Add function to allow enabling and disabling of the clock using the SCMI interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that support new API from those that just have the older protocol. SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future changes. It is placed after the functions that are present in the existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to SCMI_CLOCK_PROTOCOL so that only a single implementation of those function are needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add OPTEE_SUCCESS return codeSumit Garg2018-12-111-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-291-0/+6
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-271-0/+42
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add MM interface SVC return codes.Achin Gupta2018-11-271-0/+7
| | | | | | | | | This patch adds the Management Mode(MM) - Secure Partition Manager(SPM) SVC return codes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Fix the SPM version SVC IDSughosh Ganu2018-11-271-1/+1
| | | | | | | | | The MM_VERSION SMC call uses SMC32 calling convention. Fix the macro to reflect the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove now unused BsdLib.hArd Biesheuvel2018-11-261-212/+0
| | | | | | | | | The last remaining users of the BdsLib.h header reside in the edk2-platforms tree, and so it has been copied there. This allows us to remove the original from ArmPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add APIs to communicate with OP-TEESumit Garg2018-10-301-0/+88
| | | | | | | | | | | | | | | Add following APIs to communicate with OP-TEE pseudo/early TAs: 1. OpteeInit 2. OpteeOpenSession 3. OpteeCloseSession 4. OpteeInvokeFunc Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add support for GICv4Sami Mujawar2018-10-121-3/+19
| | | | | | | | | | | | | | | | | | | | Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-012-0/+42
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMtlLib: fix prototype inconsistency in MtlWaitUntilChannelFreeArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | | Align the prototype of ArmMtlLib's MtlWaitUntilChannelFree () with the one in the ArmMtlNullLib implementation (rather than the other way around, since edk2-platforms has a conflicting implementation as well) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add reenable hook to ArmGenericTimerCounterLibArd Biesheuvel2018-04-261-0/+6
| | | | | | | | | | | | | | In preparation of selectively reinstating the timer enable quirk for Xen that we removed in commit 411a373ed642 ("ArmPkg/TimerDxe: remove workaround for KVM timer handling"), add a ArmGenericTimerReenableTimer() library function to ArmGenericTimerCounterLib that we will populate for Xen only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Julien Grall <julien.grall@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
* ArmPkg: Introduce SCMI protocolGirish Pathak2018-04-234-0/+684
| | | | | | | | | | | | | | | | | | | This change introduces a new SCMI protocol driver for Arm systems. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure various clocks available on the platform e.g. HDLCD clock on the Juno platforms. Whereas performance management protocol allows adjustment of various performance domains. Currently this is used to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: MTL Library interface and Null library implementationGirish Pathak2018-04-231-0/+137
| | | | | | | | | | | | | Upcoming new component ArmPkg/Drivers/ArmScmiDxe is dependent on platform specific ArmMtlLib library implementation, however in order to be able to build the ArmScmiDxe component outside of the context of a particular platform, this change adds Null implementation of the ArmMtlLib along with ARM MTL library header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Library/ArmLib: add ArmWriteSctlrMichael Zimmermann2018-01-151-0/+6
| | | | | | | | | | This currently isn't needed by anything in the edk2 tree but it's useful for externally maintained platforms which have to set this register e.g. to disable alignment aborts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLEPeicong Li2017-11-071-0/+8
| | | | | | | | | | | | | | | | | | | Flash region needs to be set as cacheable (write back) to increase performance, if PEI is still XIP on flash or DXE FV is decompressed from flash FV. However some ARM platforms do not support to set flash as inner shareable since flash is not normal DDR memory and it will not respond to cache snoop request, which will causes system hang after MMU is enabled. So we need a new ARM memory region attribute WRITE_BACK_NONSHAREABLE for flash region on these platforms specifically. This attribute will set the region as write back but not inner shared. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Peicong Li <lipeicong@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Include: Add ArmSvcLib header file.Supreeth Venkatesh2017-10-061-0/+46
| | | | | | | | | | ArmSvcLib header file to specify the SVC arguments structure and function prototype to trigger an SVC call. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add SVC function IDs for Management Mode.Supreeth Venkatesh2017-10-061-0/+43
| | | | | | | | | | | | | | SVCs are in the range 0xC4000060 - 0xC400007f. The functions available to the secure MM partition: 1. Signal completion of MM event handling. 2. Set/Get memory attributes for a memory region at runtime. 3. Get version number of secure partition manager. Also, it defines memory attributes required for set/get operations. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add standard SMC function IDs for MM interface.Supreeth Venkatesh2017-10-061-1/+19
| | | | | | | | | | | | | | | | | | | | This patch adds a list of function IDs that fall under the standard SMC range as defined in [1] SMCs associated with Management Mode are in the range 0xC4000040 - 0xC400005f (64 bit) and 0x84000040 - 0x8400005f (32 bit). The function(s) available to the normal world: 1. Request services from the secure MM environment using MM_COMMUNICATE. It also defines MM return codes. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocolArd Biesheuvel2017-10-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Tidy GIC code before changes.Evan Lloyd2017-10-051-16/+7
| | | | | | | | | | | | | | | | | | | This change is purely cosmetic, to tidy some code before change. Mods involve: Re-order #includes Reformat comments. Use ns consistently (always "100ns" not sometimes "100 nS") Split overlength code lines. Make protocol functions STATIC. Remove "Horor vacui" comments. Rationalize GIC register address calculations Replace explicit test and assert with ASSERT_EFI_ERROR. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove UncachedMemoryAllocationLibArd Biesheuvel2017-08-311-665/+0
| | | | | | | | | | | | | | Now that ArmDmaLib can take care of its own memory allocation needs, let's get rid of UncachedMemoryAllocationLib entirely. This forces platforms to declare the required semantics (non-cache coherent DMA, whichever way it is implemented), rather than using uncached memory allocations directly, which may not always be the right choice, and prevents sharing of drivers between platforms if one is cache coherent and the other is not. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Move IS_DEVICE_PATH_NODE for sharingJun Nie2017-08-011-0/+3
| | | | | | | | Move IS_DEVICE_PATH_NODE into header to share it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add CNTHCTL_EL2 support functionsSami Mujawar2017-05-221-1/+11
| | | | | | | | | | Added helper functions for reading and writing the CNTHCTL_EL2 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove ArmCpuLib header and implementationsArd Biesheuvel2017-04-061-28/+0
| | | | | | | | Remove ArmCpuLib entirely. It is no longer used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/ArmMmuLib: remove VirtualMask arg from ArmSetMemoryAttributesArd Biesheuvel2017-03-071-2/+1
| | | | | | | | | | | | | We no longer make use of the ArmMmuLib 'feature' to create aliased memory ranges with mismatched attributes, and in fact, it was only wired up in the ARM version to begin with. So remove the VirtualMask argument from ArmSetMemoryAttributes()'s prototype, and remove the dead code that referred to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: move ARM version of SetMemoryAttributes to ArmMmuLibArd Biesheuvel2017-03-072-0/+14
| | | | | | | | | | | | | | | ... where it belongs, since AARCH64 already keeps it there, and non DXE users of ArmMmuLib (such as DxeIpl, for the non-executable stack) may need its functionality as well. While at it, rename SetMemoryAttributes to ArmSetMemoryAttributes, and make any functions that are not exported STATIC. Also, replace an explicit gBS->AllocatePages() call [which is DXE specific] with MemoryAllocationLib::AllocatePages(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CpuDxe: remove VirtualUncachedPages protocol and implementationArd Biesheuvel2017-02-231-60/+0
| | | | | | | | | | Virtual uncached pages are simply pages that are aliased using mismatched attributes, which is not allowed by the ARM architecture. So remove the protocol and its implementation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managedArd Biesheuvel2017-02-221-0/+12
| | | | | | | | | In preparation of enabling stack alignment checking, which is mandated by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissionsArd Biesheuvel2017-02-211-0/+4
| | | | | | | | | | | | | | Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel2017-01-205-196/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg: remove LoadConstantXxx() asm macrosArd Biesheuvel2016-10-283-73/+0
| | | | | | | | This is ancient cruft that is no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg RVCT: add ADRL/LDRL macro equivalentsArd Biesheuvel2016-10-281-0/+20
| | | | | | | | | | | | | | | The GCC ARM builds have access to ADRL/LDRL macros that emit relative symbol references, i.e., references that do not require fixing up at load time (or FV generation time for XIP modules) Implement equivalent functionality for RVCT: note that this does not use movw/movt pairs, but the more compatible add/add/add or add/add/ldr sequences (which Clang does not support, unfortunately, hence the use of movw/movt for the GCC toolchain family) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AsmMacroIoLib: force word alignment for functionsArd Biesheuvel2016-09-211-0/+1
| | | | | | | | | Without an explicit .align directive, the Clang assembler defaults to no alignment, which may result in instructions appearing misaligned in the final executable. So use word alignment in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: introduce ASM_FUNC, MOV32/MOV64 and ADRL/LDRL macrosArd Biesheuvel2016-08-112-1/+42
| | | | | | | | | | | | | | | | This introduces the ASM_FUNC() macro to annotate function entry points in assembler files. This allows us to add additional metadata that marks a function entry point as a function, and allows us to emit a .section directive for each function, which makes it possible for the linker to drop unreferenced code. In addition, introduce a couple of utility macros that we can use to clean up the code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AsmMacroIoLib: remove unused obsolete MMIO and other asm macrosArd Biesheuvel2016-08-112-267/+0
| | | | | | | | | | | | | | This removes the various Mmio ASM macros that are not used anywhere in the code, and removes some variants of LoadConstant... () that are not used anywhere either. Note that these MmioXxx() implementations are unrelated to the C versions defined in MdePkg. These are strictly intended for use in assembler, and no such uses remain. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add Cortex-A72 CPU typeJeremy Linton2016-07-281-0/+1
| | | | | | | | Add the Cortex-A72 CPU type which is used in JunoR2. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: avoid type promotion in TCR_EL1 assignmentArd Biesheuvel2016-07-131-78/+62
| | | | | | | | | | | | | | | | | | | | | | Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1") introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30), and ORs it into the value to be written into TCR_EL1 (if executing at EL1). Since the constant is implicitly typed as signed int, and has the sign bit set, the promotion that occurs when casting to UINT64 results in a TCR value that has bits [63:32] all set, which includes mostly RES0 bits but also the TBIn, AS and IPS fields. So explicitly redefine all TCR related constants as 'unsigned long' types, using the UL suffix. To avoid confusion in the future, the inappropriately named VTCR_EL23_xxx constants have the leading V removed, and the actual VTCR_EL2 related constants are dropped, given that we never configure stage 2 translation in UEFI. Reported-by: Vishal Oliyil Kunnil <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLibArd Biesheuvel2016-07-071-38/+0
| | | | | | | | | | | | Switch all users of ArmLib that depend on the MMU routines to the new, separate ArmMmuLib. This needs to occur in one go, since the MMU routines are removed from ArmLib build at the same time, to prevent conflicting symbols. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* ArmPkg: introduce ArmMmuLib library classArd Biesheuvel2016-07-071-0/+65
| | | | | | | | | Introduce the library class ArmMmuLib, which encapsulates the functionality to set up and modify page table entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1Ard Biesheuvel2016-06-231-2/+3
| | | | | | | | | | | | Reassign all interrupts to non-secure Group-1 if the GIC has its DS (Disable Security) bit set. In this case, it is safe to assume that we own the GIC, and that no other firmware has performed any configuration yet, which means it is up to us to reconfigure the interrupts so they can be taken by the non-secure firmware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: don't invalidate entire I-cache on range operationArd Biesheuvel2016-05-121-2/+8
| | | | | | | | | | | Instead of cleaning the data cache to the PoU by virtual address and subsequently invalidating the entire I-cache, invalidate only the range that we just cleaned. This way, we don't invalidate other cachelines unnecessarily. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/AArch64Mmu: disable MMU during page table manipulationsArd Biesheuvel2016-04-141-0/+6
| | | | | | | | | | | | | | | | | | | | On ARM, manipulating live page tables is cumbersome since the architecture mandates the use of break-before-make, i.e., replacing a block entry with a table entry requires an intermediate step via an invalid entry, or TLB conflicts may occur. Since it is not generally feasible to decide in the page table manipulation routines whether such an invalid entry will result in those routines themselves to become unavailable, use a function that is callable with the MMU off (i.e., a leaf function that does not access the stack) to perform the change of a block entry into a table entry. Note that the opposite should never occur, i.e., table entries are never coalesced into block entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
* ArmPkg/AsmMacroIoLibV8: remove undocumented assumption from ELx macrosArd Biesheuvel2016-03-221-8/+8
| | | | | | | | | | | | | | | The macros EL1_OR_EL2() and EL1_OR_EL2_OR_EL3() allow conditional execution of assembly sequences based on the current exception level, by jumping to caller supplied labels 1f, 2f or 3f. However, the jump to 1f is actually a fallthrough, which means the EL1 code needs to follow right after the macro invocation, and the 1f label is ignored. So let's fix this by making all jumps explicit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene2016-03-161-0/+5
| | | | | | | | | Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Configure TTBCR registerEvan Lloyd2016-03-031-1/+7
| | | | | | | | | | | | | Architecturally, the TTBCR register value is undefined at reset for Non-Secure. On some platforms the reset value for TTBCR is not zero and this causes a data abort exception once the MMU is enabled. This patch configures the TTBCR register to enable translation table walk using TTBR0. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 08:57:35 +0000