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* ArmPkg: Fix Ecc error 8005 for SCMI_CLOCK_RATE_FORMATPierre Gondois2021-04-152-7/+7
| | | | | | | | | | | | This patch fixes the following Ecc reported error: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_CLOCKPierre Gondois2021-04-151-5/+5
| | | | | | | | | | | | This patch fixes the following Ecc reported error: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Fix Ecc error 8005 for SCMI_MESSAGE_ID_BASEPierre Gondois2021-04-151-5/+5
| | | | | | | | | | | | This patch fixes the following Ecc reported error: Variable name does not follow the rules: 1. First character should be upper case 2. Must contain lower case characters 3. No white space characters 4. Global variable name must start with a 'g' Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Fix Ecc error 7008 for OPTEE_MESSAGE_PARAMPierre Gondois2021-04-151-4/+7
| | | | | | | | | | This patch fixes the following Ecc reported error: Complex types should be typedef-ed The error is due to the a nested structure declaration. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Fix Ecc error 7008 for SCMI_CLOCK_RATEPierre Gondois2021-04-151-4/+10
| | | | | | | | | | This patch fixes the following Ecc reported error: Complex types should be typedef-ed The error is due to the a nested structure declaration. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Rename include guard in ArmGicLib.hPierre Gondois2021-04-151-4/+4
| | | | | | | | | | | | | | Edk2 coding standard states that: "Names starting with one or two underscores, such as _MACRO_GUARD_FILE_NAME_H_, must not be used." Ref: https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/ 5_source_files/53_include_files# 5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Fix Ecc error 8001 in ChipsetPierre Gondois2021-04-154-14/+14
| | | | | | | | | | | | | | | | | | | This patch fixes the following Ecc reported error: Only capital letters are allowed to be used for #define declarations Edk2 coding standard stating that: "Names starting with one or two underscores, such as _MACRO_GUARD_FILE_NAME_H_, must not be used." the include guard of ArmCortexA5x.h is also updated. Ref: https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/ 5_source_files/53_include_files# 5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Allow FF-A calls to get memory region's attributesAchin Gupta2021-02-231-0/+18
| | | | | | | | | | Allow getting memory region's permissions using either of the Firmware Framework(FF-A) ABI transport or through the earlier used SVC calls. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Co-developed-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Add macros for SPM version with FF-A support enabledSughosh Ganu2021-02-231-0/+3
| | | | | | | | | | | Declare the values of SPM major and minor versions as macros with FF-A enabled, which can be used in the module for checking the SPM version compatibility. These SPM major and minor version numbers are mandated for having support for the Firmware Framework(FF-A) feature enabled. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Add macros for SPM versionSughosh Ganu2021-02-231-0/+3
| | | | | | | | | Declare the values of SPM major and minor versions as macros which can be used in the module for checking the SPM version compatibility. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/ArmSvcLib: Return x4-x7 in output parametersAchin Gupta2021-02-231-2/+8
| | | | | | | | | | | The Arm SMC calling convention standard v1.2 allows 8 input and output parameter registers. The FF-A specification relies on this communication. This patch extends the number of output registers returned by ArmCallSvc() to match this convention. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg/IndustryStandard: Add barebones FF-A headerAchin Gupta2021-02-231-0/+23
| | | | | | | | | This patch adds a rudimentary header file with defines for FF-A ABIs that will be used as the transport between S-EL0 and the SPM Signed-off-by: Achin Gupta <achin.gupta@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Update OemGetChassisType function to return MISC_CHASSIS_TYPERebecca Cran2021-02-231-5/+3
| | | | | | | | Update OemGetChassisType in OemMiscLib to return MISC_CHASSIS_TYPE instead of EFI_STATUS, which matches other OemMiscLib functions. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Rename some functions and parameters in OemMiscLibRebecca Cran2021-02-231-7/+7
| | | | | | | | | | | o Rename 'mHiiHandle' parameter in OemUpdateSmbiosInfo to 'HiiHandle'. o Rename 'Offset' parameter in OemUpdateSmbiosInfo to 'Field'. o Rename OemGetProcessorMaxSockets to OemGetMaxProcessors. o Rename OemIsSocketPresent to OemIsProcessorPresent. o Update Universal/Smbios to follow the changes to OemMiscLib. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Fix ordering of return type and EFIAPI specifier in OemMiscLibRebecca Cran2021-02-231-7/+7
| | | | | | | The return type should be on the line before any EFIAPI specifier. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Add Library/OemMiscLib.hRebecca Cran2021-02-081-0/+167
| | | | | | | | | OemMiscLib.h provides the interface which platforms should implement to interact with the SmbiosMiscDxe and ProcessorSubClassDxe drivers to update SMBIOS tables. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Acked-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Add helper to read CCIDX statusRebecca Cran2021-02-081-0/+11
| | | | | | | | Add a helper function to determine CCIDX support. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Add definition of the maximum cache level in ARMv8-ARebecca Cran2021-02-081-0/+4
| | | | | | | | | | The ARM Architecture Reference Manual for ARMv8-A defines up to seven levels of cache, L1 through L7. Define MAX_ARM_CACHE_LEVEL to be 7. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Add register encoding definition for MMFR2Rebecca Cran2021-02-081-0/+4
| | | | | | | | | | Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Add ARM SMC Architecture functions to ArmStdSmc.hRebecca Cran2021-02-081-0/+16
| | | | | | | | | The ARM SMC Architecture functions were missing from ArmStdSmc.h. Add them, based on the SMC Calling Convention version 1.2 specification. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg/ArmGicLib: Add ArmGicSetInterruptPriority() helper functionQuan Nguyen2020-12-181-0/+9
| | | | | | | | | | | | | | | | According to ARM IHI 0069F, section 11.9.18 GICD_IPRIORITYR<n>, Interrupt Priority Registers, n = 0 - 254, when affinity routing is enabled for the Security state of an interrupt, GICR_IPRIORITYR<n> is used instead of GICD_IPRIORITYR<n> where n = 0 to 7 (that is, for SGIs and PPIs). As setting interrupt priority for SGIs and PPIs are handled using difference registers depends on the mode, this patch instroduces ArmGicSetInterruptPriority() helper function to handle the discrepancy. Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmLib: move ArmReadIdPfr0/1 into private header ArmV7Lib.hLeif Lindholm2020-12-181-12/+0
| | | | | | | | | | | ArmReadIdPfr0 () and ArmReadIdPfr1 () are now used only inside ArmLib. Remove the prototypes from the public header to discourage new id register accessor additions, and direct id register access in general. Move them into local header Arm/ArmV7Lib.h. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg: add ArmHasSecurityExtensions () helper functionLeif Lindholm2020-12-181-0/+17
| | | | | | | | | | | | | Create a helper function to eliminate direct feature register reading. Returns BOOLEAN True if the CPU implements the Security extensions, otherwise returns BOOL False. This function is only implemented for ARM, not AArch64. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmLib: add ArmHasGicSystemRegisters () helper functionLeif Lindholm2020-12-181-0/+18
| | | | | | | | | | | | Create a helper function to eliminate direct feature register reading, which gets messy in code shared between ARM/AArch64. Returns BOOLEAN True if the CPU implements the GIC System Register Interface (any version), otherwise returns BOOL False. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/CpuDxe: move PageAttributeToGcdAttribute() out of ArmMmuLibArd Biesheuvel2020-04-021-5/+0
| | | | | | | | | The routine PageAttributeToGcdAttribute() is exported by ArmMmuLib but only ever used in the implementation of CpuDxe. So let's move the function there and make it STATIC. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: move set/way helper functions into private headerArd Biesheuvel2020-03-051-18/+0
| | | | | | | | | | | | | The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate routines that operate on the entire cache hierarchy, as exposed by ArmLib. The latter routines will be deprecated soon, so move the helpers out of ArmLib.h and into a private header so they are safe from abuse. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Fix various typosAntoine Cœur2019-07-041-2/+2
| | | | | | | Fix various typos in ArmPkg. Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0933-231/+33
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidationArd Biesheuvel2019-01-291-1/+2
| | | | | | | | | | | | | | | | | | | Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: delete unused ArmTrustZoneSmc.hLeif Lindholm2019-01-211-161/+0
| | | | | | | | | | | | | ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h contains definitions contradicting the SMC Calling Convention (ARM DEN0028B). It also has no users in public trees. So delete before it can cause damage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ArmPkg/ArmScmiDxe: Add clock enable functionJeff Brasen2018-12-211-0/+197
| | | | | | | | | | | | | | | | Add function to allow enabling and disabling of the clock using the SCMI interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that support new API from those that just have the older protocol. SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future changes. It is placed after the functions that are present in the existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to SCMI_CLOCK_PROTOCOL so that only a single implementation of those function are needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add OPTEE_SUCCESS return codeSumit Garg2018-12-111-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-291-0/+6
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-271-0/+42
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add MM interface SVC return codes.Achin Gupta2018-11-271-0/+7
| | | | | | | | | This patch adds the Management Mode(MM) - Secure Partition Manager(SPM) SVC return codes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Fix the SPM version SVC IDSughosh Ganu2018-11-271-1/+1
| | | | | | | | | The MM_VERSION SMC call uses SMC32 calling convention. Fix the macro to reflect the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove now unused BsdLib.hArd Biesheuvel2018-11-261-212/+0
| | | | | | | | | The last remaining users of the BdsLib.h header reside in the edk2-platforms tree, and so it has been copied there. This allows us to remove the original from ArmPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add APIs to communicate with OP-TEESumit Garg2018-10-301-0/+88
| | | | | | | | | | | | | | | Add following APIs to communicate with OP-TEE pseudo/early TAs: 1. OpteeInit 2. OpteeOpenSession 3. OpteeCloseSession 4. OpteeInvokeFunc Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add support for GICv4Sami Mujawar2018-10-121-3/+19
| | | | | | | | | | | | | | | | | | | | Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-012-0/+42
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMtlLib: fix prototype inconsistency in MtlWaitUntilChannelFreeArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | | Align the prototype of ArmMtlLib's MtlWaitUntilChannelFree () with the one in the ArmMtlNullLib implementation (rather than the other way around, since edk2-platforms has a conflicting implementation as well) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: add reenable hook to ArmGenericTimerCounterLibArd Biesheuvel2018-04-261-0/+6
| | | | | | | | | | | | | | In preparation of selectively reinstating the timer enable quirk for Xen that we removed in commit 411a373ed642 ("ArmPkg/TimerDxe: remove workaround for KVM timer handling"), add a ArmGenericTimerReenableTimer() library function to ArmGenericTimerCounterLib that we will populate for Xen only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Julien Grall <julien.grall@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
* ArmPkg: Introduce SCMI protocolGirish Pathak2018-04-234-0/+684
| | | | | | | | | | | | | | | | | | | This change introduces a new SCMI protocol driver for Arm systems. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure various clocks available on the platform e.g. HDLCD clock on the Juno platforms. Whereas performance management protocol allows adjustment of various performance domains. Currently this is used to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: MTL Library interface and Null library implementationGirish Pathak2018-04-231-0/+137
| | | | | | | | | | | | | Upcoming new component ArmPkg/Drivers/ArmScmiDxe is dependent on platform specific ArmMtlLib library implementation, however in order to be able to build the ArmScmiDxe component outside of the context of a particular platform, this change adds Null implementation of the ArmMtlLib along with ARM MTL library header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Library/ArmLib: add ArmWriteSctlrMichael Zimmermann2018-01-151-0/+6
| | | | | | | | | | This currently isn't needed by anything in the edk2 tree but it's useful for externally maintained platforms which have to set this register e.g. to disable alignment aborts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLEPeicong Li2017-11-071-0/+8
| | | | | | | | | | | | | | | | | | | Flash region needs to be set as cacheable (write back) to increase performance, if PEI is still XIP on flash or DXE FV is decompressed from flash FV. However some ARM platforms do not support to set flash as inner shareable since flash is not normal DDR memory and it will not respond to cache snoop request, which will causes system hang after MMU is enabled. So we need a new ARM memory region attribute WRITE_BACK_NONSHAREABLE for flash region on these platforms specifically. This attribute will set the region as write back but not inner shared. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Peicong Li <lipeicong@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Include: Add ArmSvcLib header file.Supreeth Venkatesh2017-10-061-0/+46
| | | | | | | | | | ArmSvcLib header file to specify the SVC arguments structure and function prototype to trigger an SVC call. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add SVC function IDs for Management Mode.Supreeth Venkatesh2017-10-061-0/+43
| | | | | | | | | | | | | | SVCs are in the range 0xC4000060 - 0xC400007f. The functions available to the secure MM partition: 1. Signal completion of MM event handling. 2. Set/Get memory attributes for a memory region at runtime. 3. Get version number of secure partition manager. Also, it defines memory attributes required for set/get operations. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add standard SMC function IDs for MM interface.Supreeth Venkatesh2017-10-061-1/+19
| | | | | | | | | | | | | | | | | | | | This patch adds a list of function IDs that fall under the standard SMC range as defined in [1] SMCs associated with Management Mode are in the range 0xC4000040 - 0xC400005f (64 bit) and 0x84000040 - 0x8400005f (32 bit). The function(s) available to the normal world: 1. Request services from the secure MM environment using MM_COMMUNICATE. It also defines MM return codes. [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0060a/DEN0060A_ARM_MM_Interface_Specification.pdf. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmGicDxe: Expose HardwareInterrupt2 protocolArd Biesheuvel2017-10-051-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | The existing HardwareInterrupt protocol lacked a means to configure the level/edge properties of an interrupt. The new HardwareInterrupt2 protocol introduced this capability. This patch updates the GIC drivers to provide the new interfaces. The changes comprise: Update to use HardwareInterrupt2 protocol Additions to register info in ArmGicLib.h Added new functionality (GetTriggerType and SetTriggerType) The requirement for this change derives from a problem detected on ARM Juno boards, but the change is of generic (ARM) relevance. This commit is in response to review on the mailing list and, as suggested there, rolls Girish's updates onto Ard's original example. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Tested-by: Girish Pathak <girish.pathak@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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