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* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09273-1898/+273
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/SemiHostingDebugLib: Add new APIsBret Barkelew2019-04-021-5/+101
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Fix writes to GICv3 GICD_IROUTER<n> regSami Mujawar2019-02-261-2/+2
| | | | | | | | | | | | | | According to ARM Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0, GICD_IROUTER<n> is a 64-bit register. Fixed code to use 64 bit MMIO write operations so that the Aff3 value (bits [39:32]) is written to GICD_IROUTER<n>. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reported-by: Carl van Schaik <carl@cog.systems> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: get rid of needless TLB invalidationArd Biesheuvel2019-01-294-21/+22
| | | | | | | | | | | | | | | | | | | Currently, we always invalidate the TLBs entirely after making any modification to the page tables. Now that we have introduced strict memory permissions in quite a number of places, such modifications occur much more often, and it is better for performance to flush only those TLB entries that are actually affected by the changes. At the same time, relax some system wide data synchronization barriers to non-shared. When running in UEFI, we don't share virtual address translations with other masters, unless we are running under virt, but in that case, the host will upgrade them as appropriate (by setting an override at EL2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: trim high memory regions instead of rejecting themArd Biesheuvel2019-01-281-1/+2
| | | | | | | | | | | | | | | ArmSetMemoryAttributes() still chokes in some cases, i.e., when the length of the region exceeds 4 GB, the subtraction overflows, which results in the region being misidentified as being 32-bit addressable. Let's update the logic to trim the length to what we can address with 32 bits. This fixes the issue, and also deals with the issue where an entire region is disregarded if part of it exceeds beyond what we can map with 32 bits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: delete unused ArmTrustZoneSmc.hLeif Lindholm2019-01-211-161/+0
| | | | | | | | | | | | | ArmPkg/Include/IndustryStandard/ArmTrustZoneSmc.h contains definitions contradicting the SMC Calling Convention (ARM DEN0028B). It also has no users in public trees. So delete before it can cause damage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ArmPkg/DefaultExceptionHandlerLib: add missing UefiLib includeArd Biesheuvel2019-01-171-0/+1
| | | | | | | | | | | | Commit 31f5388006fc ("ArmPkg/DefaultExceptionHandlerLib: use console if available") added calls to AsciiPrint() to the default exception handler code, but the ARM version did not include UefiLib.h yet (even though the .INF declares it unconditionally), resulting in build breakage. So add the missing include. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: use console if availableArd Biesheuvel2019-01-163-3/+16
| | | | | | | | | | | | Print the minimal 'exception occurred' message to the console as well as to the serial port if the console is available. This makes such messages visible on systems where the console is graphical and the serial is not connected. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/DefaultExceptionHandlerLib: drop BASE variantArd Biesheuvel2019-01-163-81/+0
| | | | | | | | | | Drop the redundant BASE variant, which is no longer used anywhere now that DebugAgentSymbolsBaseLib no longer incorporates a vector table and exception handling. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib: declare the permitted usage contextArd Biesheuvel2019-01-161-2/+2
| | | | | | | | | | | Declare that this library is only usable in the context of DXE core or a DXE driver. Set the MODULE_TYPE to BASE: this only affects the prototype of the constructor (if present) but doesn't actually restrict the usage context otherwise. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DebugAgentSymbolsBaseLib: remove exception handlingArd Biesheuvel2019-01-165-662/+0
| | | | | | | | | | | | | | | | | | | | | DebugAgentSymbolsBaseLib is an optional library that is in charge of extracting debug headers from SEC and PEI_CORE images in memory so the filename and the offset in memory can be reported via the UART, allowing a developer to load debugging symbols into his debugger. Interestingly enough, DebugAgentSymbolsBaseLib is also in charge of exception handling before this duty is taken over by either the PEI core, or the CPU DXE driver when running under PrePi. Since exceptions are not actually handled at all on AArch64, and simply routed to the DefaultExceptionHandlerLib (for which a special version has been created to be usable this early), let's get rid of this dubious functionality altogether. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib AARCH64: fix out of bounds accessArd Biesheuvel2019-01-141-1/+1
| | | | | | | | | | Take care not to dereference BlockEntry if it may be pointing past the end of the page table we are manipulating. It is only a read, and thus harmless, but HeapGuard triggers on it so let's fix it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: disregard high memory when setting permissionsArd Biesheuvel2019-01-141-0/+4
| | | | | | | | | | | Ignore calls to ArmSetMemoryAttributes () when the region described is outside of the 32-bit addressable range. This memory is not mapped in the first place, and the current code does not deal with the high bits correctly, resulting in hangs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix thinko in second level page table handlingArd Biesheuvel2019-01-131-2/+2
| | | | | | | | | | | | | | | | | PopulateLevel2PageTable () is invoked for [parts of] mappings that start or end on a non-1 MB aligned address (or both). The size of the mapping depends on both the start address modulo 1 MB and the length of the mapping, but the logic that calculates this size is flawed: subtracting 'start address modulo 1 MB' could result in a negative value for the remaining length, which is obviously wrong. So instead, take either RemainLength, or the rest of the 1 MB block, whichever is smaller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Eugene Cohen <eugene@hp.com>
* ArmPkg/ArmMmuLib ARM: add missing support for non-shareable cached mappingsArd Biesheuvel2019-01-131-0/+13
| | | | | | | | | | | Commit 829633e3a82 ("ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLE") introduced support for non-shareable cached mappings to the AArch64 version of ArmMmuLib, but the ARM version was left behind, so fix that. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSoftFloatLib: drop build flags specific to GCC46/GCC47Laszlo Ersek2019-01-081-2/+0
| | | | | | | | | | | | | | | | | | | We've removed BaseTools support for GCC44..GCC47. Drop ArmPkg/ArmSoftFloatLib build flags that are specific to any of those gcc versions. (See also commit 01627dba0911, "ArmPkg/ArmSoftfloatLib: restrict -fno-tree-vrp option to GCC46 and GCC47", 2015-12-15). No GCC44..GCC47 references remain under ArmPkg after this patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1377 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* ArmPkg/ArmScmiDxe: Add clock enable functionJeff Brasen2018-12-215-0/+268
| | | | | | | | | | | | | | | | Add function to allow enabling and disabling of the clock using the SCMI interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that support new API from those that just have the older protocol. SCMI_CLOCK2_PROTOCOL also adds a version parameter to allow for future changes. It is placed after the functions that are present in the existing protocol to allow SCMI_CLOCK2_PROTOCOL to be cast to SCMI_CLOCK_PROTOCOL so that only a single implementation of those function are needed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/GenericWatchdogDxe: implement RegisterHandler() methodArd Biesheuvel2018-12-201-9/+25
| | | | | | | | | | | Even though UEFI does not appear to use it, let's implement the complete PI watchdog protocol, including handler registration, which will be invoked before the ResetSystem() runtime service when the watchdog timer expires. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/GenericWatchdogDxe: clean up the codeArd Biesheuvel2018-12-202-55/+61
| | | | | | | | | | Clean up the code, by adding missing STATIC modifiers, drop redundant casts, and get rid of the 'success handling' anti pattern in the entry point code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: take MAX_ALLOC_ADDRESS into accountArd Biesheuvel2018-12-201-1/+1
| | | | | | | | | | | | | When creating the page tables for the 1:1 mapping, ensure that we don't attempt to map more than what is architecturally permitted when running with 4 KB pages, which is 48 bits of VA. This will be reflected in the value of MAX_ALLOC_ADDRESS once we override it for AArch64, so use that macro instead of MAX_ADDRESS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/DefaultExceptionHandlerLib ARM: avoid endless loop in RELEASE buildsArd Biesheuvel2018-12-191-0/+2
| | | | | | | | | | | | | Ensure that we prevent the CPU from proceeding after having taken an unhandled exception on a RELEASE build, which does not contain the ASSERT() which ensures this on DEBUG and NOOPT builds. Retain the code following the deadloop so that we can keep going when running in a debugger. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: drop ArmBds remnant Pcds from .decLeif Lindholm2018-12-191-20/+0
| | | | | | | | | | | | | | | | The following Pcds - gArmTokenSpaceGuid.PcdArmLinuxSpinTable - gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset - gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment remained defined, without actual users. So get rid of them. One reference to be deleted separately from edk2-platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove redundant _ARM_PLATFORM_FLAGS overridesArd Biesheuvel2018-12-151-3/+0
| | | | | | | | | | Our default is already armv7-a, so no need to rewrite the PLATFORM_FLAGS for that. Also, setting -mfpu=neon is not entirely inappropriate, since NEON is not mandatory under v7. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/OpteeLib: Add OPTEE_SUCCESS return codeSumit Garg2018-12-111-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add dummy RPC handlerSumit Garg2018-12-062-7/+30
| | | | | | | | | Add dummy RPC handler for RPCs that are not implemented as control should be returned back to OP-TEE in case any RPC is invoked. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: handle unmapped sections when updating permissionsArd Biesheuvel2018-12-031-2/+6
| | | | | | | | | | | | | The ARM ArmMmuLib code currently does not take into account that setting permissions on a region should take into account that a region may not be mapped yet to begin with. So when updating a section descriptor whose old value is zero, pass in the address explicitly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: handle unmapped section in GetMemoryRegion()Ard Biesheuvel2018-12-031-0/+3
| | | | | | | | | | | | | | | | GetMemoryRegion() is used to obtain the attributes of an existing mapping, to permit permission attribute changes to be optimized away if the attributes don't actually change. The current ARM code assumes that a section mapping or a page mapping exists for any region passed into GetMemoryRegion(), but the region may be unmapped entirely, in which case the code will crash. So check if a section mapping exists before dereferencing it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
* ArmPkg/CpuPei: base GCD memory space size on CPU's PA rangeArd Biesheuvel2018-11-292-2/+1
| | | | | | | | | | | | Derive the size of the GCD memory space map directly from the CPU's information registers rather than from the PcdPrePiCpuMemorySize PCD, which will be removed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: take the CPU supported maximum PA space into accountArd Biesheuvel2018-11-293-8/+9
| | | | | | | | | | | | In preparation of dropping PcdPrePiCpuMemorySize entirely, base the maximum size of the identity map on the capabilities of the CPU. Since that may exceed what is architecturally permitted when using 4 KB pages, take MAX_ADDRESS into account as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-294-0/+39
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: fix StandaloneMmMmuLib subdirectory caseLeif Lindholm2018-11-272-1/+1
| | | | | | | | | While this isn't the only Aarch64 directory in the tree, let's keep from adding more of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmPkg.dsc: move ArmMmuStandaloneMmLib.inf to AARCH64 sectionArd Biesheuvel2018-11-271-1/+1
| | | | | | | | | ArmMmuStandaloneMmLib.inf cannot be built for ARM so move it to the [Components.AARCH64] section in ArmPkg.dsc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: Add MMU Library suitable for use in S-EL0.Achin Gupta2018-11-275-0/+265
| | | | | | | | | | | | | | | | | | | | | | | The Standalone MM environment runs in S-EL0 in AArch64 on ARM Standard Platforms. Privileged firmware e.g. ARM Trusted Firmware sets up its architectural context including the initial translation tables for the S-EL1/EL0 translation regime. The MM environment will still request ARM TF to change the memory attributes of memory regions during initialization. The Standalone MM image is a FV that encapsulates the MM foundation and drivers. These are PE-COFF images with data and text segments. To initialise the MM environment, Arm Trusted Firmware has to create translation tables with sane default attributes for the memory occupied by the FV. This library sends SVCs to ARM Trusted Firmware to request memory permissions change for data and text segments. This patch adds a simple MMU library suitable for execution in S-EL0 and requesting memory permissions change operations from Arm Trusted Firmware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add MM interface SVC return codes.Achin Gupta2018-11-271-0/+7
| | | | | | | | | This patch adds the Management Mode(MM) - Secure Partition Manager(SPM) SVC return codes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Fix the SPM version SVC IDSughosh Ganu2018-11-271-1/+1
| | | | | | | | | The MM_VERSION SMC call uses SMC32 calling convention. Fix the macro to reflect the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Drivers: Add EFI_MM_COMMUNICATION_PROTOCOL DXE driver.Achin Gupta2018-11-273-0/+456
| | | | | | | | | | | | | | | | | | | | PI v1.5 Specification Volume 4 defines Management Mode Core Interface and defines EFI_MM_COMMUNICATION_PROTOCOL. This protocol provides a means of communicating between drivers outside of MM and MMI handlers inside of MM. This patch implements the EFI_MM_COMMUNICATION_PROTOCOL DXE runtime driver for AARCH64 platforms. It uses SMCs allocated from the standard SMC range defined in DEN0060A_ARM_MM_Interface_Specification.pdf to communicate with the standalone MM environment in the secure world. This patch also adds the MM Communication driver (.inf) file to define entry point for this driver and other compile related information the driver needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add PCDs needed for MM communication driver.Achin Gupta2018-11-271-0/+3
| | | | | | | | | | This patch defines PCDs to describe the base address and size of communication buffer between normal world (uefi) and standalone MM environment in the secure world. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove now unused BsdLib.hArd Biesheuvel2018-11-261-212/+0
| | | | | | | | | The last remaining users of the BdsLib.h header reside in the edk2-platforms tree, and so it has been copied there. This allows us to remove the original from ArmPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: add missing call to ExitBootServices()Ard Biesheuvel2018-11-216-6/+187
| | | | | | | | | | | | | | | | | | | | Our poor man's implementation of EnterS3WithImmediateWake () currently sets a high TPL level to disable interrupts, and simply calls the PEI entrypoint again after disabling the MMU. Unfortunately, this is not sufficient: DMA capable devices such as network controllers or USB controllers may still be enabled and writing to memory, e.g., in response to incoming network packets. So instead, do the full ExitBootServices() dance: allocate space and get the memory map, call ExitBootServices(), and in case it fails, get the memory map again and call ExitBootServices() again. This ensures that all cleanup related to DMA capable devices is performed before doing the warm reset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledgeArd Biesheuvel2018-11-152-2/+2
| | | | | | | | | | | Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses the wrong system register encoding to access ICC_IAR1, and attempted to access ICC_IAR0 instead. This results in boot time hangs both under QEMU emulation and on real hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: Fix GICv3 interrupt routing mode bugMing Huang2018-11-071-1/+1
| | | | | | | | | | | | | | | | Setting GICD_IROUTERn.IRM and GICD_IROUTERn.{Aff3,Aff2,Aff1,Aff0} at the same time is nonsensical (see 8.9.13 in the GICv3 spec, which says of GICD_IROUTERn.IRM that "When this bit is set to 1, GICD_IROUTER<n>.{Aff3,Aff2,Aff1,Aff0} are UNKNOWN"). There is also no guarantee that IRM is implemented (see GICD_TYPER.No1N which indicates whether the implementation supports this or not). Let's thus not set this bit, as we want all SPIs to be delivered to the same CPU, and not be broadcast to all of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <ming.huang@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* ArmPkg/OpteeLib: Fix compilation issues for ARM (32-bit)Sumit Garg2018-11-051-7/+7
| | | | | | | | | | Correct usage of EFI_PHYSICAL_ADDRESS (always 64-bit) vs. pointers (depending on architecture). Reported-by: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add APIs to communicate with OP-TEESumit Garg2018-10-304-0/+535
| | | | | | | | | | | | | | | Add following APIs to communicate with OP-TEE pseudo/early TAs: 1. OpteeInit 2. OpteeOpenSession 3. OpteeCloseSession 4. OpteeInvokeFunc Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add support for GICv4Sami Mujawar2018-10-123-21/+46
| | | | | | | | | | | | | | | | | | | | Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: fix hotkey of boot optionHaojian Zhuang2018-08-231-1/+1
| | | | | | | | | Fix the parameter in EfiBootManagerAddKeyOptionVariable (). Otherwise, the hotkey of boot option won't be registered correctly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bitMarcin Wojtas2018-08-032-2/+4
| | | | | | | | | | | | | | | | According to the SBSA specification the Watchdog Compare Register is split into two separate 32bit registers. EDK2 code uses a single 64bit transaction to update them, which can be problematic, depending on the SoC implementation and could result in unpredictable behavior. Fix this by modifying WatchdogWriteCompareRegister routine to use two consecutive 32bit writes to the Watchdog Compare Register Low and High, using new dedicated macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-016-0/+124
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBDS: Implement PlatformBootManagerUnableToBootRuiyu Ni2018-07-271-1/+17
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Removing ipf which is no longer supported from edk2.chenc22018-06-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmScmiDxe: Dynamically allocate buffer for protocol idsGirish Pathak2018-06-223-12/+21
| | | | | | | | | | | | Dynamically allocate the buffer to receive the SCMI protocol list. This makes MAX_PROTOCOLS redundant, so it is removed. It also fixes one minor code alignment issue and removes an unused macro PROTOCOL_MASK. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-13 22:35:44 +0000