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* ArmPkg/Include: Fix the SPM version SVC IDSughosh Ganu2018-11-271-1/+1
| | | | | | | | | The MM_VERSION SMC call uses SMC32 calling convention. Fix the macro to reflect the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Drivers: Add EFI_MM_COMMUNICATION_PROTOCOL DXE driver.Achin Gupta2018-11-273-0/+456
| | | | | | | | | | | | | | | | | | | | PI v1.5 Specification Volume 4 defines Management Mode Core Interface and defines EFI_MM_COMMUNICATION_PROTOCOL. This protocol provides a means of communicating between drivers outside of MM and MMI handlers inside of MM. This patch implements the EFI_MM_COMMUNICATION_PROTOCOL DXE runtime driver for AARCH64 platforms. It uses SMCs allocated from the standard SMC range defined in DEN0060A_ARM_MM_Interface_Specification.pdf to communicate with the standalone MM environment in the secure world. This patch also adds the MM Communication driver (.inf) file to define entry point for this driver and other compile related information the driver needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Add PCDs needed for MM communication driver.Achin Gupta2018-11-271-0/+3
| | | | | | | | | | This patch defines PCDs to describe the base address and size of communication buffer between normal world (uefi) and standalone MM environment in the secure world. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove now unused BsdLib.hArd Biesheuvel2018-11-261-212/+0
| | | | | | | | | The last remaining users of the BdsLib.h header reside in the edk2-platforms tree, and so it has been copied there. This allows us to remove the original from ArmPkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: add missing call to ExitBootServices()Ard Biesheuvel2018-11-216-6/+187
| | | | | | | | | | | | | | | | | | | | Our poor man's implementation of EnterS3WithImmediateWake () currently sets a high TPL level to disable interrupts, and simply calls the PEI entrypoint again after disabling the MMU. Unfortunately, this is not sufficient: DMA capable devices such as network controllers or USB controllers may still be enabled and writing to memory, e.g., in response to incoming network packets. So instead, do the full ExitBootServices() dance: allocate space and get the memory map, call ExitBootServices(), and in case it fails, get the memory map again and call ExitBootServices() again. This ensures that all cleanup related to DMA capable devices is performed before doing the warm reset. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledgeArd Biesheuvel2018-11-152-2/+2
| | | | | | | | | | | Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses the wrong system register encoding to access ICC_IAR1, and attempted to access ICC_IAR0 instead. This results in boot time hangs both under QEMU emulation and on real hardware. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: Fix GICv3 interrupt routing mode bugMing Huang2018-11-071-1/+1
| | | | | | | | | | | | | | | | Setting GICD_IROUTERn.IRM and GICD_IROUTERn.{Aff3,Aff2,Aff1,Aff0} at the same time is nonsensical (see 8.9.13 in the GICv3 spec, which says of GICD_IROUTERn.IRM that "When this bit is set to 1, GICD_IROUTER<n>.{Aff3,Aff2,Aff1,Aff0} are UNKNOWN"). There is also no guarantee that IRM is implemented (see GICD_TYPER.No1N which indicates whether the implementation supports this or not). Let's thus not set this bit, as we want all SPIs to be delivered to the same CPU, and not be broadcast to all of them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <ming.huang@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* ArmPkg/OpteeLib: Fix compilation issues for ARM (32-bit)Sumit Garg2018-11-051-7/+7
| | | | | | | | | | Correct usage of EFI_PHYSICAL_ADDRESS (always 64-bit) vs. pointers (depending on architecture). Reported-by: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/OpteeLib: Add APIs to communicate with OP-TEESumit Garg2018-10-304-0/+535
| | | | | | | | | | | | | | | Add following APIs to communicate with OP-TEE pseudo/early TAs: 1. OpteeInit 2. OpteeOpenSession 3. OpteeCloseSession 4. OpteeInvokeFunc Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add support for GICv4Sami Mujawar2018-10-123-21/+46
| | | | | | | | | | | | | | | | | | | | Updated Redistributor base calculation to allow for the fact that GICv4 has 2 additional 64KB frames (for VLPI and a reserved frame). The code now tests the VLPIS bit in the GIC Redistributor Type Register (GICR_TYPER) and calculates the Redistributor granularity accordingly. The code changes are: GICR_TYPER register fields, etc, added to the header. Loop updated to pay attention to GICR_TYPER.Last. Derive frame "stride" size from GICR_TYPER.VLPIS. Note: The assumption is that the redistributors are adjacent for all CPUs. However this may not be the case for NUMA systems. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: fix hotkey of boot optionHaojian Zhuang2018-08-231-1/+1
| | | | | | | | | Fix the parameter in EfiBootManagerAddKeyOptionVariable (). Otherwise, the hotkey of boot option won't be registered correctly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bitMarcin Wojtas2018-08-032-2/+4
| | | | | | | | | | | | | | | | According to the SBSA specification the Watchdog Compare Register is split into two separate 32bit registers. EDK2 code uses a single 64bit transaction to update them, which can be problematic, depending on the SoC implementation and could result in unpredictable behavior. Fix this by modifying WatchdogWriteCompareRegister routine to use two consecutive 32bit writes to the Watchdog Compare Register Low and High, using new dedicated macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Add initial OpteeLib implementationSumit Garg2018-08-016-0/+124
| | | | | | | | | | | This is initial version of OP-TEE library that provides api's to communicate with OP-TEE OS (Trusted OS based on ARM TrustZone) via secure monitor calls. Currently it provides basic api to detect OP-TEE presence via UID matching. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBDS: Implement PlatformBootManagerUnableToBootRuiyu Ni2018-07-271-1/+17
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Removing ipf which is no longer supported from edk2.chenc22018-06-292-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmScmiDxe: Dynamically allocate buffer for protocol idsGirish Pathak2018-06-223-12/+21
| | | | | | | | | | | | Dynamically allocate the buffer to receive the SCMI protocol list. This makes MAX_PROTOCOLS redundant, so it is removed. It also fixes one minor code alignment issue and removes an unused macro PROTOCOL_MASK. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmScmiDxe: Fix ASSERT error in SCMI DXEGirish Pathak2018-06-222-21/+23
| | | | | | | | | | | | | | | | | | | | | This change fixes a bug in the SCMI DXE which is observed with the upcoming release of the SCP firmware. The PROTOCOL_ID_MASK (0xF) which is used to generate an index in the ProtocolInitFxns is wrong because protocol ids can be anywhere in 0x10 - 15 or 0x80 - FF range. This mask generates the same index for two different protocols e.g. for protocol ids 0x10 and 0x90, which causes duplicate initialization of a protocol resulting in a failure. This change removes the use of PROTOCOL_ID_MASK and instead uses a list of protocol ids and their initialization functions to identify a supported protocol and initialize it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead of table baseChris Co2018-06-211-1/+1
| | | | | | | | | | | | | Mva address calculation should use the left-shifted current section index instead of the left-shifted table base address. Using the table base address here has the side-effect of potentially causing an access violation depending on the base address value. Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Christopher Co <christopher.co@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memoryArd Biesheuvel2018-06-212-13/+3
| | | | | | | | | | | | Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contentsArd Biesheuvel2018-06-211-12/+0
| | | | | | | | | | | | | | | | | | | Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by page and section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMtlLib: fix prototype inconsistency in MtlWaitUntilChannelFreeArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | | Align the prototype of ArmMtlLib's MtlWaitUntilChannelFree () with the one in the ArmMtlNullLib implementation (rather than the other way around, since edk2-platforms has a conflicting implementation as well) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmPkg.dsc: enable NOOPT build targetArd Biesheuvel2018-06-181-1/+1
| | | | | | | | | Enable to NOOPT build target so we can build this package with optimizations disabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm rebootArd Biesheuvel2018-06-153-2/+32
| | | | | | | | | | | | | | Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: call ProcessCapsules() only onceArd Biesheuvel2018-06-152-27/+60
| | | | | | | | | | | | | ARM platforms have no restriction on when a system firmware update capsule can be applied, and so it is not necessary to call ProcessCapsules() twice. So let's drop the first invocation that occurs before EndOfDxe, and rewrite the second call so that all capsule updates will be applied when the console is up and able to provide progress feedback. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/CompilerIntrinsicsLib: fix GCC8 warning for __aeabi_memcpy aliasesMichael Zimmermann2018-06-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | This was the warning (shown for __aeabi_memcpy, __aeabi_memcpy4 and __aeabi_memcpy8): ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c:42:6: error: '__aeabi_memcpy8' alias between functions of incompatible types 'void(void*, const void *, size_t)' {aka 'void(void *, const void *, unsigned int)'} and 'void *(void *, const void *, size_t)' {aka 'void *(void *, const void *, unsigned int)'} [-Werror=attribute-alias] void __aeabi_memcpy8(void *dest, const void *src, size_t n); ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c:19:7: note: aliased declaration here void *__memcpy(void *dest, const void *src, size_t n) The problem is the different return type (void vs void*). So reshuffle the code so the prototypes match between the aliases. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> [ardb: change prototype of internal __memcpy() and drop extra wrapper] Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmDisassemblerLib: fix check for MSR instructionMichael Zimmermann2018-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | GCC8 reported it with the following warning: ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c: In function 'DisassembleArmInstruction': ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c:397:30: error: bitwise comparison always evaluates to false [-Werror=tautological-compare] if ((OpCode & 0x0db00000) == 0x03200000) { This condition tries to be true for both the immediate and the register version of the MSR instruction. They get identified inside the if-block using the variable I, which contains the value of bit 25. The problem with the comparison reported by GCC is that the bitmask excludes bit 25, while the value requires it to be set to one: 0x0db00000: 0000 11011 0 11 00 00 0000 000000000000 0x03200000: 0000 00110 0 10 00 00 0000 000000000000 ^ So the solution is to just don't require that bit to be set, because it gets checked later using 'I', which results in the following value: 0x01200000: 0000 00010 0 10 00 00 0000 000000000000 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: load platform boot optionsHaojian Zhuang2018-06-052-0/+105
| | | | | | | | | | | | | Make platform driver to create predefined boot options and related hot keys. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: Fix bug in Generic Watchdog driverAlexeiFedorov2018-04-301-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c, the following functions: WatchdogWriteOffsetRegister() WatchdogWriteCompareRegister() WatchdogEnable() WatchdogDisable() provide write access to ARM Generic Watchdog registers and use the values returned by MmioWrite32() and MmioWrite64() as EFI_STATUS return codes. Because MmioWriteXY() return the value passed as its write parameter, Generic Watchdog access functions can spuriously return error codes which are different from EFI_SUCCESS, e.g. the following call Status = WatchdogWriteOffsetRegister (MAX_UINT32); if (EFI_ERROR (Status)) { return Status; } will return MAX_UINT32 defined in MdePkg/Include/Base.h as #define MAX_UINT32 ((UINT32)0xFFFFFFFF) This commit declares all the functions listed above as VOID and removes the code for checking their return values. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Reviewed-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: add reenable hook to ArmGenericTimerCounterLibArd Biesheuvel2018-04-264-0/+23
| | | | | | | | | | | | | | In preparation of selectively reinstating the timer enable quirk for Xen that we removed in commit 411a373ed642 ("ArmPkg/TimerDxe: remove workaround for KVM timer handling"), add a ArmGenericTimerReenableTimer() library function to ArmGenericTimerCounterLib that we will populate for Xen only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Julien Grall <julien.grall@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
* ArmPkg: Introduce SCMI protocolGirish Pathak2018-04-2317-1/+2748
| | | | | | | | | | | | | | | | | | | This change introduces a new SCMI protocol driver for Arm systems. The driver currently supports only clock and performance management protocols. Other protocols will be added as and when needed. Clock management protocol is used to configure various clocks available on the platform e.g. HDLCD clock on the Juno platforms. Whereas performance management protocol allows adjustment of various performance domains. Currently this is used to evaluate performance of the Juno platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: MTL Library interface and Null library implementationGirish Pathak2018-04-234-1/+273
| | | | | | | | | | | | | Upcoming new component ArmPkg/Drivers/ArmScmiDxe is dependent on platform specific ArmMtlLib library implementation, however in order to be able to build the ArmScmiDxe component outside of the context of a particular platform, this change adds Null implementation of the ArmMtlLib along with ARM MTL library header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/TimerDxe: remove workaround for KVM timer handlingArd Biesheuvel2018-04-192-11/+0
| | | | | | | | | | | | | | | | When we first ported EDK2 to KVM/arm, we implemented a workaround for the quirky timer handling on the KVM side. This has been fixed in Linux commit f120cd6533d2 ("KVM: arm/arm64: timer: Allow the timer to control the active state") dated 23 June 2014, which was incorporated into Linux release 4.3. So almost 4 years later, it should be safe to drop this workaround on the EDK2 side. This reverts commit b1a633434ddc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/CpuDxe: order CpuDxe after ArmGicDxe via protocol depexLaszlo Ersek2018-04-122-3/+1
| | | | | | | | | | | | | | | | | | | | | | Commit 61a7b0ec634f ("ArmPkg/Gic: force GIC driver to run before CPU arch protocol driver", 2018-02-06) explains why CpuDxe should be dispatched after ArmGicDxe. To implement the ordering, we should use a regular protocol depex rather than the less flexible AFTER opcode. ArmGicDxe installs gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid as one of the last actions on its entry point stack; either of those is OK for CpuDxe to wait for. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmGicDxe: annotate protocol usage in "ArmGicDxe.inf"Laszlo Ersek2018-04-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | "ArmGicDxe.inf" currently does not document how the protocols in the [Protocols] section are used. Such comments help us analyze behavior, so let's add them now. - gHardwareInterruptProtocolGuid and gHardwareInterrupt2ProtocolGuid are always produced on the InterruptDxeInitialize() -> (GicV2DxeInitialize() | GicV3DxeInitialize()) -> InstallAndRegisterInterruptService() call path. - gEfiCpuArchProtocolGuid is consumed in the CpuArchEventProtocolNotify() protocol notify callback. (Technically this is "conditional"; however the firmware cannot work without architectural protocols, so we can call it unconditional.) While at it, drop the gArmGicDxeFileGuid comment from FILE_GUID; we're going to make that GUID uninteresting soon. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/TimerDxe: Add ISB for timer compare value reloadHeyi Guo2018-03-151-0/+1
| | | | | | | | | | | | If timer interrupt is level sensitive, reloading timer compare register has a side effect of clearing GIC pending status, so a "ISB" is needed to make sure this instruction is executed before enabling CPU IRQ, or else we may get spurious timer interrupts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/TimerDxe: Always perform an EOI, even for spurious interruptsMarc Zyngier2018-03-061-6/+4
| | | | | | | | | | | | | | | | | | | The generic timer driver only EOIs the timer interrupt if the ISTATUS bit is set. This is completely fine if you pretend that spurious interrupts do not exist. But as a matter of fact, they do, and the first one will leave the interrupt activated at the GIC level, making sure that no other interrupt can make it anymore. Making sure that each interrupt Ack is paired with an EOI is the way to go. Oh, and enabling the interrupt each time it is taken is completely pointless. We entered this function for a good reason... Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* ArmPkg/Library/CompilerIntrinsicsLib: Enable VS2017/ARM buildsPete Batard2018-02-077-32/+185
| | | | | | | | | | | | | | | Introduce CRT assembly replacements for __rt_sdiv, __rt_udiv, __rt_udiv64, __rt_sdiv64, __rt_srsh (by reusing the RVCT code) as well as memcpy and memset. For MSFT compatibility, some of the code needs to be explicitly forced to ARM, and the /oldit assembly flag needs to be added. Also, while RVCT_ASM_EXPORT macro invocations have been removed, the replacement code is designed to be as close as possible to the one that would have been generated if using the macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Gic: force GIC driver to run before CPU arch protocol driverArd Biesheuvel2018-02-065-25/+54
| | | | | | | | | | | | | | | | | | | | | | | Currently, the GIC driver has a static dependency on the CPU arch protocol driver, so it can register its IRQ handler at init time. This means there is a window between dispatch of the CPU driver and dispatch of the GIC driver where any unexpected GIC state may trigger an interrupt which we are not set up to handle yet. Note that this is even the case if we enter UEFI with interrupts disabled at the CPU, given that any TPL manipulation involving TPL_HIGH_LEVEL will unconditionally enable IRQs at the CPU side regardless of whether they were enabled to begin with (but only as soon as the CPU arch protocol is actually installed) So let's reorder the GIC driver with the CPU driver, and let it run its initialization that puts the GIC into a known state before enabling interrupts. Move its installation of its IRQ handler to a protocol notify callback on the CPU arch protocol so that it runs as soon as it becomes available. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Marc Zyngier <marc.zyngier@arm.com>
* ArmPkg: delete references to unused guids/Pcds from CpuDxeLeif Lindholm2018-02-062-3/+0
| | | | | | | | | | gEfiDebugSupportPeriodicCallbackProtocolGuid and PcdCpuDxeProduceDebugSupport are referred to from CpuDxe. Delete references from .inf and .h. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Library/ArmLib: add ArmWriteSctlrMichael Zimmermann2018-01-154-0/+22
| | | | | | | | | | This currently isn't needed by anything in the edk2 tree but it's useful for externally maintained platforms which have to set this register e.g. to disable alignment aborts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmMmuLib ARM: fix page size granularity in initial MMU settingMichael Zimmermann2017-12-201-17/+23
| | | | | | | | | | | | | | | | | From what I can see this bug dates back to the commit from 2011 where support for this was added: 2cf4b60895f8a The first problem is that PopulateLevel2PageTable overflows the translation table buffer because it doesn't verify that the size actually fits within one level 2 page table. The second problem is that the loop in FillTranslationTable doesn't care about the PhysicalBase or the RemainLength and always substracts one section size from RemainLength. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/PlatformBootManagerLib: add missing newlineArd Biesheuvel2017-12-111-1/+1
| | | | | | | | | Add a missing newline to the version string output that is displayed on the serial console, or the next line will be appended to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/PlatformBootManagerLib: print firmware version to consoleArd Biesheuvel2017-12-082-0/+26
| | | | | | | | | | | | If gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString is set to a non-empty string, print it to the console at boot. Note that this is independent of DEBUG/RELEASE or graphical vs serial console, although we do attempt to stay clear of the logo and progress bar in graphical mode, by printing it top center. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmExceptionLib: Add implementation of new APIJian J Wang2017-12-081-0/+33
| | | | | | | | | | | | | | | | | | | | | | | This patch add implementation of following new API introduced into CpuExceptionHandlerLib. Since this lib hasn't support Stack Guard and stack switch, the new method just calls original InitializeCpuExceptionHandlers. EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitDataEx OPTIONAL ); Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: remove BdsLib and remaining ARM BDS related PCDsArd Biesheuvel2017-11-268-2309/+0
| | | | | | | | | With the last user FdtPlatformDxe removed, we can finally get rid of the last bit of ARM BDS related cruft. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: remove unused ArmGicSecLib library implementationArd Biesheuvel2017-11-264-155/+2
| | | | | | | | | | | This module is not used anywhere under edk2 or edk2-platforms, so let's remove it. This removes the only dependency on ArmPlatformLib from ArmPkg. While at it, remove a mention of ArmPlatformPkg from a comment in the .dec file as well. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg: move RVCT PLATFORM_FLAGS override into ArmHvcLib/ArmSmcLibArd Biesheuvel2017-11-163-2/+6
| | | | | | | | | | | | | Currently, each ARM platform built with RVCT that uses ArmHvcLib or ArmSmcLib needs to specify a CPU target that implements both the security and virtualization extensions, so that the assembler does not choke on the 'hvc' and 'smc' instructions in ArmHvcLib/ArmSvcLib. Let's move these overrides into the module .INFs so we can lift this requirement at the platform side. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHAREABLEPeicong Li2017-11-072-0/+12
| | | | | | | | | | | | | | | | | | | Flash region needs to be set as cacheable (write back) to increase performance, if PEI is still XIP on flash or DXE FV is decompressed from flash FV. However some ARM platforms do not support to set flash as inner shareable since flash is not normal DDR memory and it will not respond to cache snoop request, which will causes system hang after MMU is enabled. So we need a new ARM memory region attribute WRITE_BACK_NONSHAREABLE for flash region on these platforms specifically. This attribute will set the region as write back but not inner shared. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Peicong Li <lipeicong@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmSvcLib: Add ArmSvcLib implementation.Supreeth Venkatesh2017-10-065-0/+156
| | | | | | | | | | | | | | | | This patch adds a library that enables invocation of SVCs from Exception Level EL0. It will be used by the Standalone MM environment to request services from a software running in a privileged EL e.g. ARM Trusted Firmware. The library is derived directly from Arm SMC Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> [ardb: assign frame pointer (AArch64) keep stack alignment (ARM)] Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/Include: Add ArmSvcLib header file.Supreeth Venkatesh2017-10-062-0/+47
| | | | | | | | | | ArmSvcLib header file to specify the SVC arguments structure and function prototype to trigger an SVC call. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 12:22:48 +0000