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* ArmPkg: Fix Ecc error 8001 in ChipsetPierre Gondois2021-04-151-5/+5
| | | | | | | | | | | | | | | | | | | This patch fixes the following Ecc reported error: Only capital letters are allowed to be used for #define declarations Edk2 coding standard stating that: "Names starting with one or two underscores, such as _MACRO_GUARD_FILE_NAME_H_, must not be used." the include guard of ArmCortexA5x.h is also updated. Ref: https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/ 5_source_files/53_include_files# 5-3-5-all-include-file-contents-must-be-protected-by-a-include-guard Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPlatformPkg: Fix Ecc error 8001Pierre Gondois2021-04-156-34/+34
| | | | | | | | | | | | | | | This patch fixes the following Ecc reported error: File header doesn't exist File header comment missing the ""Copyright"" Even though a copyright is present in the header file, the leading '*' char prevents the Ecc tool from detecting it. According to the edk2 coding specifcation, section 5.2.3 "File Heading", there should not be leading '*' char. Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPlatformPkg/PrePeiCore: replace set/way cache ops with by-VA onesArd Biesheuvel2020-03-043-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the temporary RAM region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled, which will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmPlatformPkg/PrePeiCore: enable VFP at startupArd Biesheuvel2020-01-143-0/+7
| | | | | | | | | | | | | While the alternative PEI-less SEC implementation in PrePi already takes the EnableVFP PCD into account, the PrePeiCore code does not, and so we may end up triggering synchronous exception when code attempts to use FP or SIMD registers, which is permitted on AARCH64 by the spec. So enable the VFP as early as feasible if the associated PCD is set. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: list module-internal header files in INF [Sources]Laszlo Ersek2019-07-232-0/+2
| | | | | | | | | | | | | | | | | | The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file", 2019-06-10) logs some (non-fatal) warnings about unlisted internal header files. List those files explicitly. Note: header files are added in lexicographical order only if the underlying INF file already keeps the [Sources] and [LibraryClasses] sections in lexicographical order. Otherwise, header files are added in rough "logical" order. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Fix various typosAntoine Cœur2019-07-041-1/+1
| | | | | | | Fix various typos in ArmPlatformPkg. Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0918-126/+18
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: clear frame pointer in startup codeArd Biesheuvel2018-11-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up the stack in the startup code and jumping into C code for the first time, ensure that the frame pointer register is cleared so that backtraces terminate correctly. Otherwise, output like the below is shown when encountering an exception on a DEBUG build: Synchronous Exception at 0x0000000078A14780 PC 0x000078A14780 (0x000078A00000+0x00014780) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A10634 (0x000078A00000+0x00010634) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A11CF0 (0x000078A00000+0x00011CF0) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A11DD0 (0x000078A00000+0x00011DD0) [ 0] ArmVeNorFlashDxe.dll PC 0x00007BC9D87C (0x00007BC98000+0x0000587C) [ 1] PartitionDxe.dll PC 0x00007BC99B3C (0x00007BC98000+0x00001B3C) [ 1] PartitionDxe.dll PC 0x00007F362F50 (0x00007F359000+0x00009F50) [ 2] DxeCore.dll PC 0x00007BD63BB0 (0x00007BD5B000+0x00008BB0) [ 3] BdsDxe.dll PC 0x00007BD6EE00 (0x00007BD5B000+0x00013E00) [ 3] BdsDxe.dll PC 0x00007BD67C70 (0x00007BD5B000+0x0000CC70) [ 3] BdsDxe.dll PC 0x00007F3724F0 (0x00007F359000+0x000194F0) [ 4] DxeCore.dll PC 0x00004008FC30 PC 0x000040090130 PC 0x5800F6025800F5E1 Recursive exception occurred while dumping the CPU state which is rather unhelpful, given that this prevent the remaining debug output from being printed (register dump, stack dump, fault related system registers etc) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PrePeiCoreMPCore: use a unique GUIDArd Biesheuvel2017-12-081-1/+1
| | | | | | | | | | | PrePeiCoreMPCore reuses the GUID of its unicore sibling, which is usually fine, given that platforms never include both. However, it prevents us from creating a package .DSC that does include both, so update the GUID to a fresh one. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PrePeiCore: seed temporary stack before entering PEI coreArd Biesheuvel2017-11-095-0/+26
| | | | | | | | | | | | | | | | | | | | | | DEBUG builds of PEI code will print a diagnostic message regarding the utilization of temporary RAM before switching to permanent RAM. For example, Total temporary memory: 16352 bytes. temporary memory stack ever used: 4820 bytes. temporary memory heap used for HobList: 4720 bytes. Tracking stack utilization like this requires the stack to be seeded with a known magic value, and this needs to occur before entering C code, given that it uses the stack. Currently, only Nt32Pkg appears to implement this feature, but it is useful nonetheless, so let's wire it up for PrePeiCore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Timer access for non-secure EL1/0Sami Mujawar2017-05-221-1/+8
| | | | | | | | | | | | | | | According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A"; the primary CPU must be configured such that 'Timer access must be provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.' This commit adds this missing set-up to the PrePi and PrePeiCore modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2016-09-081-5/+5
| | | | | | | | | | | According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PrePeiCore: switch to ASM_FUNC() asm macroArd Biesheuvel2016-08-115-71/+18
| | | | | | | | | | | Annotate functions with ASM_FUNC() so that they are emitted into separate sections. While we're at it, replace some inefficient uses of LoadConstantToReg() Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg RVCT: drop dependency on GCC macro libraryArd Biesheuvel2016-08-112-12/+4
| | | | | | | | | | | The RVCT .asm files include AsmMacroIoLib.h only for the definition of LoadConstantToReg (), which makes it tedious to make change to that file without the risk of making the RVCT assembler unhappy. So simply replace LoadConstantToReg() with mov32, which does the right thing in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: fixups for 64-bit pointersLeendert van Doorn2016-03-253-3/+3
| | | | | | | | | | | | | This retypes some stack base PCD as 64-bit, and fixes up a number of references to 64-bit PCDs (including the retypes ones), to use the correct PcdGet64() accessors. Note that, in the case of FixedPcdGet64, this does not actually caused any problems, since that resolves to an immediate value. But the generic PcdGetxx accessors should be typed according to the size of the PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> [ard.biesheuvel: fixed up some instances in the 32-bit ARM code] Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: Fix stack switch bug after commit 7945b29Heyi Guo2015-12-101-4/+7
| | | | | | | | | | | | | | This is the complementary patch for the commit 7945b29, which strictly aligns temporary heap size and temporary stack size, but does not do the same thing when switching stack and heap to permanent memory, and then it may cause fatal data corruption like PHIT HOB lost and stack pointer unaligned. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19213 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PrePeiCore: use explicit UINTN cast in VOID* arithmeticArd Biesheuvel2015-12-082-2/+2
| | | | | | | | | | | RVCT does not like the arithmetic involving a VOID* pointer that was introduced in SVN r19163, so use explicit casts instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19172 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PrePeiCore: adhere to architectural stack alignment requirementArd Biesheuvel2015-12-082-14/+6
| | | | | | | | | | | | Instead of using fuzzy arithmetic with a hardcoded stack alignment value of 0x4, use the symbolic constant CPU_STACK_ALIGNMENT (which is at least 8 bytes, btw) to round the temporary stack base and size. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19163 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: remove global variable allocation from lowlevel initArd Biesheuvel2015-11-277-52/+3
| | | | | | | | | | | | Now that we dropped all ArmPlatformGlobalVariableLib dependencies, there is no longer a need to allocate and clear out the global variable region in the PrePeiCore init code. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18994 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: add missing entries to AArch64 vector tableArd Biesheuvel2015-11-271-0/+40
| | | | | | | | | | | | | | | | | The PrePeiCore vector table for AArch64 mode is only half populated. However unlikely, if exceptions from lower exception levels are ever taken, they should be reported correctly, rather than causing a recursive undefined instruction fault on the zero padding that was introduced by commit SVN r18904 ("ArmPkg/ArmPlatformPkg: position vectors relative to base"). So add the missing entries, and wire them up to the default handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18976 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland2015-11-191-14/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: constify PPI globalsArd Biesheuvel2015-08-071-5/+5
| | | | | | | | | | | | | | | Since PrePeiCore's .text section contains an AARCH64 exception vector table, its 2 KB alignment propagates to other sections as well. Since this is a SEC module, it should not have any writable data in the first place, so change some non-const PPI globals to const. The resulting binary has no .data section at all, which saves 2 KB in the XIP image. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18188 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.Leif Lindholm2014-11-113-6/+6
| | | | | | | | | | | | | | Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Removed unused PcdArmPrimaryCoreOlivier Martin2014-09-011-3/+1
| | | | | | | | | | | | This PCD has been replaced by ArmPlatformIsPrimaryCore() function. Althrough this PCD is still used in some occasions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16026 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: remove GIC related PCDs from unicoreArd Biesheuvel2014-09-011-3/+0
| | | | | | | | | | | | | | | Remove the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase from PrePeiCoreUniCore.inf, as they are not in fact used by the module. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16014 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Replace tabs by spaces for indentationRonald Cron2014-08-261-1/+1
| | | | | | | | | | | | | | | Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Removed trailing spacesRonald Cron2014-08-1910-81/+81
| | | | | | | | | | | | Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Force the SEC modules to be 2K aligned for AArch64Olivier Martin2014-07-151-3/+4
| | | | | | | | | | | | | | | The AArch64 Vector Table must be aligned on a 2K boundary. The FDF specification does not support 2K alignment but support 4K. A clear comment has been added to help integrator to understand why the assertion fails when porting to a new AArch64 platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Returned the InterruptId in ArmGicAcknowledgeInterrupt()Olivier Martin2014-07-041-5/+6
| | | | | | | | | | | | | | | | The InterruptId has a different width for GicV2 and GicV3 (respectively 10bit and 24bit). The function prototype has been changed to return this value to make the caller GIC architecture version independent. Otherwise, we would have need to expose a different mask to allow the caller to retrieve this value from the read register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15628 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGic: Move out the EndOfInterrupt from the interrupt acknowledgementOlivier Martin2014-07-041-1/+7
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15619 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Use .8byte instead of .dword for pointersBrendan Jackman2014-05-081-1/+1
| | | | | | | | | | | | Clang doesn't recognise .dword Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15510 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman2014-05-083-4/+4
| | | | | | | | | | | | This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman2014-05-082-8/+8
| | | | | | | | | | | | Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Tidy assembler codeOlivier Martin2014-03-011-3/+0
| | | | | | | | | | | | - Fixed typo - Removed unreachable 'dead' loop Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Replace single dead loop.Olivier Martin2014-03-012-11/+4
| | | | | | | | | | | | | | Several assembler macros use a loop at the label "dead" to trap an error. This is difficult to debug as there is no indication of how one arrived at the loop. This change replaces dead with distinct loops locally in the macro, which means the cause of the hang is detectable to the debugger. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: PrePei Cache disable and invalidate.Olivier Martin2013-08-061-15/+14
| | | | | | | | | | | | - Disable data cache on all cores. - Do not clean caches as there might be junk in them, invalidate only. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14527 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Added Aarch64 supportHarry Liebel2013-07-188-2/+361
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14489 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Removed the non-used PCD PcdGicPrimaryCoreIdOlivier Martin2013-07-172-8/+0
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Removed the check on the CpuId to release the secondary ↵Olivier Martin2013-07-171-3/+2
| | | | | | | | | | | | | | | | | cores from their mailbox spinning The idea is to remove the PCD PcdGicPrimaryCoreId to make the port easier (and also to allow changing the primary boot CPU without adding more platform specific code to UEFI). There is a risk the mailboxes contain garbage at boot time. But it should be easy enough to clear the mailboxes when starting UEFI to workaround this limitation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14477 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatform/ArmPlatformLib: Introduced ArmPlatformPeiBootAction()oliviermartin2013-05-102-0/+8
| | | | | | | | | | | | | | | | This function allows platform to do any specific actions prior to the start the PEI phase. For instance, this function could be used by some platforms to initialize clocks that are required at the early stage of the PEI phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14347 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Replaced the macro GetCorePositionFromMpId() by the ↵oliviermartin2013-05-102-6/+12
| | | | | | | | | | | | | ArmPlatformGetCorePosition() Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14346 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()oliviermartin2013-05-105-20/+20
| | | | | | | | | | | | | | | | Checking if a core if the primary/boot core used to be done with the macro IS_PRIMARY_CORE(). Some platforms exposes configuration registers to change the primary core. Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows some flexibility in the way to check the primary core. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Moved ARMv7 specific files to a 'Arm' subdirectoryoliviermartin2013-03-1211-65/+96
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14182 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Fixed coding style and typosoliviermartin2013-03-121-2/+2
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14179 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AsmMacroIoLib: Renamed 'GetCorePositionInStack' macro into ↵oliviermartin2012-07-042-2/+2
| | | | | | | | | | 'GetCorePositionFromMpId' Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13493 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGicLib: Replaced 'ArmGicAcknowledgeSgiFrom' by ↵oliviermartin2012-05-022-4/+16
| | | | | | | | | | | | | | | | | | 'ArmGicAcknowledgeInterrupt' The function 'ArmGicAcknowledgeSgiFrom' was actually acknowledging Interrupts (and not only SGIs). ArmPkg/ArmGicLib: Introduced the PCD PcdGicPrimaryCoreId This PCD defines the Id of the primary core in the GIC. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13259 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGicLib: Changed ArmGicSendSgiTo() to allow to send a specific SGIoliviermartin2012-05-022-2/+3
| | | | | | | | Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13258 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Renamed and Invoked earlier ArmPlatformNormalInitialize()oliviermartin2012-05-021-0/+3
| | | | | | | | | | | | | - ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize() - Make the function be called at the early stage of the PEI phase as some platforms require their interconnects or clocks to be initialize before any access to Timers or UARTs. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg: Updated the stack setup to have the same geometry between ↵oliviermartin2012-02-282-76/+58
| | | | | | | | | | | | the Secure and Normal World Having a similar setup reduces the error during the MPCore stack setup. The stack setup is described on this wikipage: https://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPlatformPkg/Stack git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13058 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/PrePeiCore: Ensured the size is 8-byte alignedoliviermartin2012-02-272-6/+14
| | | | | | | | | Once divided by 2, the size should be 4-byte aligned to ensure the stack pointer is 4-byte aligned. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13044 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-21 17:43:24 +0000