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* ArmPlatformPkg: remove PL180 SD controller driverArd Biesheuvel2020-05-055-776/+0
| | | | | | | | | | | | The PL180 SD host controller driver is only used on emulated ARM platforms, uses an obsolete version of the MMC host protocol and does not adhere to the UEFI driver model. It has been moved into edk2-platforms alongside the only platforms that use it, so we can drop it from the EDK2 core repository. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* EmbeddedPkg: rename gEfiMmcHostProtocolGuid to gEmbeddedMmcHostProtocolGuidArd Biesheuvel2020-04-302-2/+2
| | | | | | | | | | | | In EDK2, identifiers carrying the EFI prefix are reserved for ones that are defined in the UEFI or PI specifications. Since the MMC host protocol defined in EmbeddedPkg is not the one that the UEFI spec defines, and given the confusion around this, let's rename it to from gEfiMmcHostProtocolGuid to gEmbeddedMmcHostProtocolGuid. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPlatformPkg/ArmPlatformPkg.dsc: Add missing componentsMichael Kubacki2020-03-251-0/+3
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2575 The following components are currently missing from the [Components] section of ArmPlatformPkg.dsc: * ArmPlatformPkg/Library/HdLcd/HdLcd.inf * ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf This commit includes the components in the package DSC build. Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA onesArd Biesheuvel2020-03-053-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the UEFI memory region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled. (This will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again.) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Pete Batard <pete@akeo.ie> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPlatformPkg/PrePi: fix IS_XIPAndrei Warkentin2020-03-051-1/+1
| | | | | | | | | | This wasn't correctly testing for FD to be outside RAM, when RAM base immediately follows the FD. This is part of some cleanup for RPi4 in edk2-platform. Signed-off-by: Andrei Warkentin <awarkentin@vmware.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PrePeiCore: replace set/way cache ops with by-VA onesArd Biesheuvel2020-03-043-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache maintenance operations by set/way are only intended to be used in the context of on/offlining a core, while it has been taken out of the coherency domain. Any use intended to ensure that the contents of the cache have made it to main memory is unreliable, since cacheline migration and non-architected system caches may cause these contents to linger elsewhere, without being visible in main memory once the MMU and caches are disabled. In KVM on Linux, there are horrid hacks in place to ensure that such set/way operations are trapped, and replaced with a single by-VA clean/invalidate of the entire guest VA space once the MMU state changes, which can be costly, and is unnecessary if we manage the caches a bit more carefully, and perform maintenance by virtual address only. So let's get rid of the call to ArmInvalidateDataCache () in the PrePeiCore startup code, and instead, invalidate the temporary RAM region by virtual address, which is the only memory region we will be touching with the caches and MMU both disabled and enabled, which will lead to data corruption if data written with the MMU off is shadowed by clean, stale cachelines that stick around when the MMU is enabled again. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmPlatformPkg/LcdGraphicsOutputDxe: add missing protocol dependencyArd Biesheuvel2020-03-041-0/+1
| | | | | | | | | | This driver depends on the gEfiCpuArchProtocolGuid protocol but does not declare it, and so this dependency gets satisfied transitively via ArmLib. However, ArmLib will drop this dependency as it does not actually use it, so declare it for LcdGraphicsOutputDxe instead. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPlatformPkg: convert LFs to CRLF, expand hard TABsLaszlo Ersek2020-03-041-328/+328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're going to switch the internal line terminators globally to LF at some point, but until then, let's use CRLF consistently. Convert source files with LFs in them to CRLF, using "unix2dos". "git show -b" prints no code changes for this patch. (I collected all the file name suffixes in this package, with: $ git ls-files -- $PACKAGE | rev | cut -f 1 -d . | sort -u | rev I eliminated those suffixes that didn't stand for text files, then blanket-converted the rest with unix2dos. Finally, picked up the actual changes with git-add.) At the same time, the following file had to undergo TAB expansion: ArmPlatformPkg/Scripts/Ds5/profile.py I used "expand -t 4", conforming to the Indentation section of PEP-8 <https://www.python.org/dev/peps/pep-0008/#indentation>. Both the CRLF conversion and the TAB expansion are motivated by "PatchCheck.py". "PatchCheck.py" is also the reason why CRLF conversion and TAB expansion have to happen in the same patch. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1659 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200227213903.13884-4-lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPlatformPkg/Ds5: Increase path length to 400Jeff Brasen2020-02-081-3/+3
| | | | | | | | Increase length of path that can be read from system from 200 to 400 to allow for longer build paths. Signed-off-by: Jeff Brasen <jbrasen@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PrePeiCore: enable VFP at startupArd Biesheuvel2020-01-143-0/+7
| | | | | | | | | | | | | While the alternative PEI-less SEC implementation in PrePi already takes the EnableVFP PCD into account, the PrePeiCore code does not, and so we may end up triggering synchronous exception when code attempts to use FP or SIMD registers, which is permitted on AARCH64 by the spec. So enable the VFP as early as feasible if the associated PCD is set. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: strip trailing whitespaceLeif Lindholm2019-10-042-2/+2
| | | | | | | Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPlatformPkg: Add missing header files in INF filePete Batard2019-09-135-0/+5
| | | | | | | | The header files are used but missing in INF, which causes warning message when building them. Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: list module-internal header files in INF [Sources]Laszlo Ersek2019-07-234-0/+4
| | | | | | | | | | | | | | | | | | The BaseTools build feature introduced for TianoCore#1804 / in commit 1fa6699e6cd4 ("BaseTools: Add a checking for Sources section in INF file", 2019-06-10) logs some (non-fatal) warnings about unlisted internal header files. List those files explicitly. Note: header files are added in lexicographical order only if the underlying INF file already keeps the [Sources] and [LibraryClasses] sections in lexicographical order. Otherwise, header files are added in rough "logical" order. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Actually disable PL031 interruptsAlexander Graf2019-07-101-2/+2
| | | | | | | | | | | | | | The PL031 interrupt mask register (IMSC) is not very clearly documented in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether interrupts are enabled, not disabled. So before this commit, we were actually *enabling* interrupts for the RTC. This patch changes the logic to instead disable interrupts when they are not disabled already. Signed-off-by: Alexander Graf <graf@amazon.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Fix various typosAntoine Cœur2019-07-048-9/+9
| | | | | | | Fix various typos in ArmPlatformPkg. Signed-off-by: Coeur <coeur@gmx.fr> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: use UINT32 epoch second counterLeif Lindholm2019-06-171-1/+2
| | | | | | | | | | | | The comments describes the device as being 32-bit: "the maximum time span is just over 136 years" then uses a UINTN to hold the value. Change to UINT32 so we don't get different behaviour for different architectures. Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
* ArmPlatformPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-09107-748/+107
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PL011SerialPortLib: use untyped PCD for register baseArd Biesheuvel2018-12-202-8/+10
| | | | | | | | | | | | | Use an untyped PCD reference for PcdSerialRegisterBase, so that the library gets built without hardcoded values, permitting modules to override the default serial port. This allows SerialDxe to use a different serial port from the one used for DEBUG output (which often gets occluded due to the console driver clearing the screen). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/SP805WatchdogDxe: switch to interrupt modeArd Biesheuvel2018-12-203-27/+80
| | | | | | | | | | | | | | | | | The SP805 watchdog driver doesn't implement the PI watchdog protocol fully, but always simply resets the system if the watchdog time runs out. However, the hardware does support the intended usage model, as long as the SP805 is wired up correctly. So let's implement interrupt based mode involving a handler that is registered by the DXE core and invoked when the watchdog runs out. In the interrupt handler, we invoke the notify function if one was registered, before calling the ResetSystem() runtime service (as per the UEFI spec) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/SP805WatchdogDxe: cosmetic cleanupArd Biesheuvel2018-12-202-56/+52
| | | | | | | | | Before fixing the SP805 driver, let's clean it up a bit. No functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/MemoryInitPeim: take MAX_ALLOC_ADDRESS into accountArd Biesheuvel2018-12-201-3/+3
| | | | | | | | | Limit the PEI memory region so it will not extend beyond what we can address architecturally when running with 4 KB pages. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PlatformPei: drop unused PCD referencesArd Biesheuvel2018-11-292-6/+0
| | | | | | | | | | Drop some PCD references that are not actually referenced from the PlatformPei code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PrePi: base GCD memory space size on CPU's PA rangeArd Biesheuvel2018-11-293-3/+1
| | | | | | | | | | | | Derive the size of the GCD memory space map directly from the CPU's information registers rather than from the PcdPrePiCpuMemorySize PCD, which will be removed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashPlatformLib: remove unused Guid member from structArd Biesheuvel2018-11-271-1/+0
| | | | | | | | | | | We no longer use per-instance GUIDs to identify NOR flash banks so there is no longer a need to define them. Drop the Guid member from the NOR_FLASH_DESCRIPTION type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* ArmPlatformPkg/NorFlashDxe: use one GUID plus index to identify flash banksArd Biesheuvel2018-11-262-3/+4
| | | | | | | | | | | | | | | | | | | | | | Currently, each flash bank controlled by ArmPlatformPkg/NorFlashDxe has its own VendorHw GUID, and instances of NorFlashPlatformLib describe each bank to the driver, along with the GUID for each. This works ok for bare metal platforms, but it would be useful for virtual platforms if we could obtain this information from a device tree, which would require us to invent GUIDs on the fly, given that the 'cfi-flash' binding does not include a GUID. So instead, let's switch to a single GUID for all flash banks, and update the driver's device path handling to include an index to identify each bank uniquely. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* ArmPlatformPkg/NorFlashDxe: prepare for devicepath format changeArd Biesheuvel2018-11-262-3/+8
| | | | | | | | | | | | | | | A subsequent patch will change the layout of devicepath nodes produced by this driver. In preparation, make some tweaks to the code to use a packed struct for the devicepath and to pass the device index to NorFlashCreateInstance(). These are cosmetic changes only, the resulting binaries should be identical. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Thomas Abraham <thomas.abraham@arm.com>
* ArmPlatformPkg: clear frame pointer in startup codeArd Biesheuvel2018-11-192-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting up the stack in the startup code and jumping into C code for the first time, ensure that the frame pointer register is cleared so that backtraces terminate correctly. Otherwise, output like the below is shown when encountering an exception on a DEBUG build: Synchronous Exception at 0x0000000078A14780 PC 0x000078A14780 (0x000078A00000+0x00014780) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A10634 (0x000078A00000+0x00010634) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A11CF0 (0x000078A00000+0x00011CF0) [ 0] ArmVeNorFlashDxe.dll PC 0x000078A11DD0 (0x000078A00000+0x00011DD0) [ 0] ArmVeNorFlashDxe.dll PC 0x00007BC9D87C (0x00007BC98000+0x0000587C) [ 1] PartitionDxe.dll PC 0x00007BC99B3C (0x00007BC98000+0x00001B3C) [ 1] PartitionDxe.dll PC 0x00007F362F50 (0x00007F359000+0x00009F50) [ 2] DxeCore.dll PC 0x00007BD63BB0 (0x00007BD5B000+0x00008BB0) [ 3] BdsDxe.dll PC 0x00007BD6EE00 (0x00007BD5B000+0x00013E00) [ 3] BdsDxe.dll PC 0x00007BD67C70 (0x00007BD5B000+0x0000CC70) [ 3] BdsDxe.dll PC 0x00007F3724F0 (0x00007F359000+0x000194F0) [ 4] DxeCore.dll PC 0x00004008FC30 PC 0x000040090130 PC 0x5800F6025800F5E1 Recursive exception occurred while dumping the CPU state which is rather unhelpful, given that this prevent the remaining debug output from being printed (register dump, stack dump, fault related system registers etc) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Removing ipf which is no longer supported from edk2.chenc22018-06-292-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: Include PL011UartClock LibUdit Kumar2018-06-152-2/+4
| | | | | | | | | This patch gets PL011 baud rate clock from pl011 uart clock lib instead of Pcd. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: PL011 Dynamic clock freq SupportUdit Kumar2018-06-135-0/+92
| | | | | | | | | | | | | | | Some platform support dynamic clocking, which is controlled by some jumper setting or hardware registers. Result of that is that PCD PL011UartClkInHz would need to be updated for frequency change. This patch implements support for dynamic frequency for PL011 uart. This patch implements default lib, which is using Pcd. Platform which needs dynamic clocking needs implement PL011UartClockLib Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: New DP500/DP550/DP650 GOP driverGirish Pathak2018-04-235-1/+702
| | | | | | | | | | | | | | | | | | | | | | This change adds support for the ARM Mali DP500/DP500/DP650 display processors using the GOP protocol. It has been tested on FVP base models + DP550 support. This change adds platform independant LcdHwLib library. A corresponding platform specific library will be submitted to edk-platforms/Platform/ARM/VExpressPkg. This change does not modify functionality provided by PL111 or HDLCD. This LcdHwLib implementation should be suitable for those platforms that implement ARM Mali DP500/DP550/DP650 replacing PL111/HDLCD. Only graphics layer of the ARM Mali DP is configured for rendering the RGB/BGR format frame buffer to satisfy the UEFI GOP requirements Other layers e.g. video layers are not configured. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Reserving framebuffer at buildGirish Pathak2018-04-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Currently framebuffer memory is either reserved in special VRAM or dynamically allocated using boot services memory allocation functions. When allocated using boot services calls the memory has to be allocated as EfiBootServicesData. Unfortunately failures have been seen with this case. There is also an unfortunate lack of control on the placement of the framebuffer. This change introduces two PCDs, PcdArmLcdFrameBufferBase and PcdArmLcdFrameBufferSize which enable build time reservation of the framebuffer, avoiding the need to allocate dynamically. This allows the framebuffer to appear as "I/O memory" outside of the normal RAM map, which is similar to the "VRAM" case. This change has no impact on current code, only enables the option of build time reservation of framebuffers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Additional display modesGirish Pathak2018-04-231-0/+60
| | | | | | | | | | | Add definitions for new display modes such as HD 720. This has no effect on existing display drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: PCD to swap red/blue format for HDLCDGirish Pathak2018-04-233-2/+16
| | | | | | | | | | | | | | | | | | | This change adds a new PCD PcdArmHdlcdSwapBlueRedSelect to swap values for HDLCD RED_SELECT and BLUE_SELECT registers on platforms where blue and red hardware lines are swapped. If set to TRUE in the platform dsc, HDLCD library will swap the values while setting RED_SELECT and BLUE_SELECT registers. The default value of the PCD is FALSE. NOTE: The motive for this is that a discrepancy in the Red/Blue lines exists between some VersatileExpress platforms. Rather than have divergent code, this build switch allows a simple, pragmatic solution. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Add PCD to select pixel formatGirish Pathak2018-04-233-38/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current HDLCD and PL111 platform libraries do not support display modes with PixelBlueGreenRedReserved8BitPerColor format, i.e. because of historical confusion, they do not support the UEFI default PixelBlueGreenRedReserved8BitPerColor format In LcdPlatformLib for PL111, LcdPlatformQueryMode returns the pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong, because that does not match the display controller's pixel format which is set to BGR in PL111Lcd LcdHwLib. Also it is not possible to configure pixel format as RGB/BGR for the display modes for a platform at build time. This change adds PcdGopPixelFormat to configure pixel format as PixelRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor or PixelBitMask. With this change, pixel format can be selected in the platform specific .dsc file for all supported display modes. Support for PixelBitMask is not implemented in PL111 or HDLCD LcdHwLib libraries, hence HDLCD and PL111 platform libraries will return error EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask. Indeed, it is not clear what selecting PixelBitMask might mean, but the option is allowed as it might suit a custom platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Redefine LcdPlatformGetTimings functionGirish Pathak2018-04-234-70/+64
| | | | | | | | | | | | | | | | The LcdPlatformGetTimings interface function takes similar sets of multiple parameters for horizontal and vertical timings which can be aggregated in a common data type. This change defines a structure SCAN_TIMINGS for this which can be used to describe both horizontal and vertical scan timings, and accordingly redefines the LcdPlatformGetTiming interface, greatly reducing the amount of data passed about. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Implement LcdIdentify function for HDLCD GOPGirish Pathak2018-04-232-1/+9
| | | | | | | | | | | | | | LcdIdentify function does not currently check presence of HDLCD controller. Implement this functionality by reading HDLCD_REG_VERSION and checking against the PRODUCT_ID field to detect presence of HDLCD controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: PL111Lcd: Combine two writes to LCDControlGirish Pathak2018-04-231-5/+1
| | | | | | | | | | | | Currenty bit LcdPwr of the LCDControl register is enabled immediately after setting other bits of the LCDControl register. This two write sequence is unnecessary. This change removes this extra write by setting LcdPwr bit along with other bits of the LcdControl register. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: PL111Lcd: Replace magic number with macroGirish Pathak2018-04-231-2/+1
| | | | | | | | | | Minor code change, replaces magic number with macro in LCD disable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: HDLCD and PL111: Update debug ASSERTSGirish Pathak2018-04-232-12/+11
| | | | | | | | | | | This change moves some ASSERTs in error handling code to improve efficiency in DEBUG build. This change also removes redundant error code returns. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Tidy Lcd code: Updated commentsGirish Pathak2018-04-235-38/+189
| | | | | | | | | | | | There is no functional modification in this change some comments are modified and a few new comments are added. This is to prevent mixing formatting changes with functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Tidy Lcd code: Coding standardGirish Pathak2018-04-236-178/+210
| | | | | | | | | | | | There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Of specific note, some invalid include guards were fixed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Rectify line endings of LcdPlatformNullLibGirish Pathak2018-04-231-92/+92
| | | | | | | | | | | This fix changes line endings of LcdPlatformNullLib.c to DOS style line endings from UNIX style line endings to meet the EDK2 coding standard. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Rectify line endings of LcdHwNullLibGirish Pathak2018-04-231-75/+75
| | | | | | | | | | | | This fix changes line endings of LcdHwNullLib.c to DOS style line endings from UNIX style line endings to meet the EDK2 coding standard. Note it also fixes an end of line whitespace. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak <girish.pathak@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PL031RealTimeClockLib: depend on gEfiCpuArchProtocolGuidLaszlo Ersek2018-04-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | The RealTimeClockLib class is declared under EmbeddedPkg, so that platforms can provide the internals for the EmbeddedPkg/RealTimeClockRuntimeDxe driver. In turn the driver produces the Real Time Clock Arch Protocol, without which UEFI drivers cannot be dispatched. The PL031RealTimeClockLib instance calls gDS->SetMemorySpaceAttributes() in the LibRtcInitialize() public function. This DXE service depends on the CPU Arch Protocol. Add it to the depex. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: depend on gEfiCpuArchProtocolGuidLaszlo Ersek2018-04-121-1/+1
| | | | | | | | | | | | | | | | | | NorFlashFvbInitialize() calls gDS->SetMemorySpaceAttributes() to mark the varstore flash region as uncached. This DXE service depends on the CPU Architectural protocol, and the DXE core is allowed to return EFI_NOT_AVAILABLE_YET if it hasn't dispatched ArmPkg/Drivers/CpuDxe earlier. Make the dependency explicit. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: cue the variable driver with NvVarStoreFormattedLaszlo Ersek2018-04-123-8/+16
| | | | | | | | | | | | | | | | | | | | | | The BEFORE depex opcode that we currently use to force ourselves in front of the variable driver cannot be combined with other depex opcodes. Replace the depex with TRUE, and signal NvVarStoreFormattedLib through the installation of "gEdkiiNvVarStoreFormattedGuid". Platforms that rely on NorFlashDxe to format the variable store (as opposed to formatting a variable store template through an FDF file, as part of the build) should hook NvVarStoreFormattedLib into the variable drivers they use, so that the latter await our cue. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: initialize varstore headers eagerlyLaszlo Ersek2018-04-123-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lazy initialization of the varstore FVB makes no longer sense at this point: - "mNorFlashInstanceTemplate.Initialize" is NULL; - in NorFlashCreateInstance(), we only set Instance->Initialize to non-NULL -- namely NorFlashFvbInitialize() -- if the FVB stands for the variable store (see "ContainVariableStorage" / "SupportFvb"); - we call Instance->Initialize() from three places: - from NorFlashWriteSingleBlock(), which is too late for the variable read service ("variable write" depends on "variable read"); - from InitializeFvAndVariableStoreHeaders(), but that is only reachable from NorFlashFvbInitialize(), i.e. recursively from Instance->Initialize() itself; - and from FvbRead(), which is never called by the variable driver, only by the FTW driver. However, the variable driver may read (not write) the memory-mapped varstore flash chip before the FTW driver is dispatched. Therefore the lazy initialization is both superfluous and insufficient. Initialize the varstore headers eagerly, before we install the FVB protocol interface. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Steve Capper <steve.capper@linaro.org> Cc: Supreeth Venkatesh <Supreeth.Venkatesh@arm.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Steve Capper <steve.capper@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/MemoryInitPeiLib: reserve rather than remove FV memoryArd Biesheuvel2018-02-281-8/+13
| | | | | | | | | | | | | | | | | Instead of completely removing the memory occupied by the primary PrePi FV from the memory map, thereby making it inaccessible to the OS, mark it as boot services data. This will ensure that the memory is left untouched by the firmware, but will release it to the OS when it calls ExitBootServices(). Note that for reasons that are not entirely clear, this only works as desired if the memory allocation HOB and the resource descriptor HOB that describe the region are identical in offset and size, and so we still need to iterate over the descriptors and split them up. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/MemoryInitPeiLib: revert "don't reserve primary FV in memory"Ard Biesheuvel2018-02-281-0/+69
| | | | | | | | | | | | | | | | Commit 8ae5fc182941 ("ArmPlatformPkg/MemoryInitPeiLib: don't reserve primary FV in memory") deleted the code that removes the memory covering the primary firmware volume from the memory map. The assumption was that this is no longer necessary now that we no longer expose compression and PE/COFF loader library code from the PrePi module to DXE core. However, the FV is still declared, and so code may attempt to access it anyway, which may cause unexpected results depending on whether the memory has been reused for other purposes in the mean time. So revert this change in preparation of dealing with this in a better way. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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