diff options
| author | Alexander Graf <graf@amazon.com> | 2019-07-10 16:53:11 +0200 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2019-07-10 18:07:31 +0100 |
| commit | 8df52631e53c73cbe5ef037155cc5b6bdc87f757 (patch) | |
| tree | e724aa7fe11bcde21eaddce0cfa2cea80d15c093 /ArmPlatformPkg | |
| parent | 7365eb2c8cf1d7112330d09918c0c67e8d0b827a (diff) | |
| download | edk2-8df52631e53c73cbe5ef037155cc5b6bdc87f757.tar.gz edk2-8df52631e53c73cbe5ef037155cc5b6bdc87f757.tar.bz2 edk2-8df52631e53c73cbe5ef037155cc5b6bdc87f757.zip | |
ArmPlatformPkg: Actually disable PL031 interrupts
The PL031 interrupt mask register (IMSC) is not very clearly documented
in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether
interrupts are enabled, not disabled.
So before this commit, we were actually *enabling* interrupts for the RTC.
This patch changes the logic to instead disable interrupts when they
are not disabled already.
Signed-off-by: Alexander Graf <graf@amazon.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPlatformPkg')
| -rw-r--r-- | ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c index b630a5cfbf..75c95985d4 100644 --- a/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c +++ b/ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -80,8 +80,8 @@ InitializePL031 ( }
// Ensure interrupts are masked. We do not want RTC interrupts in UEFI
- if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {
- MmioOr32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
+ if ((MmioRead32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != 0) {
+ MmioWrite32 (mPL031RtcBase + PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, 0);
}
// Clear any existing interrupts
|