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* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Support different PL011 reg offsetJun Nie2017-07-173-0/+33
| | | | | | | | | ZTE/SanChip version pl011 has different reg offset and bit offset for some registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: convert VExpress ResetSystemLib to ResetSystemLibLeif Lindholm2017-07-052-50/+73
| | | | | | | | | | | Since we're in the process of migrating all of the VExpress platforms to MdeModulePkg ResetSystemRuntimeDxe, convert VExpress ResetSystemLib from EfiResetSystemLib interface to the ResetSystemLib one. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: eliminate Juno gcc build warningLeif Lindholm2017-06-201-0/+1
| | | | | | | | | | | | When building without LTO, gcc incorrectly resolves the hazards for 'PciRegBase’ when inlining, leading to "may be used uninitialized" warnings (and hence build failure with -Werror). Eliminate this warning by explicitly initializing the variable to 0. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg: Timer access for non-secure EL1/0Sami Mujawar2017-05-222-2/+16
| | | | | | | | | | | | | | | According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A"; the primary CPU must be configured such that 'Timer access must be provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.' This commit adds this missing set-up to the PrePi and PrePeiCore modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: correct NumOfLba vararg type in EraseBlocks()Laszlo Ersek2017-05-181-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PI spec, Volume 3, EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.EraseBlocks(): > The variable argument list is a list of tuples. Each tuple describes a > range of LBAs to erase and consists of the following: > * An EFI_LBA that indicates the starting LBA > * A UINTN that indicates the number of blocks to erase (NB, in edk2, EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL is a typedef to EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL.) In this driver, the NumOfLba local variable is defined with type UINTN, but the TYPE argument passed to VA_ARG() is UINT32. Fix the mismatch. In addition, update the DEBUG macro invocation where NumOfLba is formatted with the %d conversion specifier: UINTN values should be converted to UINT64 and printed with %Lu or %Lx for portability between 32-bit and 64-bit. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reported-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* ArmPlatformPkg,ArmVirtPkg: delete redundant PL031 functionsLeif Lindholm2017-05-103-135/+4
| | | | | | | | | | Remove the functions now provided by TimeBaseLib from PL031RealTimeClockLib. Add TimeBaseLib resolution to ArmVirtPkg in same commit to prevent breakage. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/ArmVExpressDxe: remove FDT handling from ArmFvpDxeArd Biesheuvel2017-04-116-443/+5
| | | | | | | | | | | | | | | | | | | | | Replace the elaborate but awkward handling of FDT images using device paths and string PCDs initialized to 128 spaces with a simple scheme involving a set of builtin DTBs and a bit of runtime logic to select between them. This is sufficient for ordinary use, which makes it more suitable as reference code. Note that overriding the DTB presented to the OS can easily be done with a UEFI application that simply installs a new DTB image under the existing FDT configuration table GUID. For this module, this simply involves removing all code that is involved in deciding which platform we are running on, and for reasoning about FDT device paths. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg/ArmVExpressDxe: remove unused cruft from ArmHwDxeArd Biesheuvel2017-04-112-45/+1
| | | | | | | | | | Remove unused cruft from ArmHwDxe -- the only thing that remains is installation of the 'runaxf' shell command. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg/ArmVExpressDxe: remove ARM supportArd Biesheuvel2017-04-113-103/+0
| | | | | | | | | | The 32-bit ARM support in this driver is unused, and thus untested. So let's just remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg/EblCmdLib: remove dependency on deprecated ARM BdsLibArd Biesheuvel2017-04-112-2/+48
| | | | | | | | | | The EBL alternative shell depends indirectly on the deprecated ARM BdsLib via EblCmdLib, which only uses a single helper function that can easily be cloned. So clone it, and remove the dependency. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAMArd Biesheuvel2017-04-062-9/+6
| | | | | | | | | | | | | | | | | Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAMArd Biesheuvel2017-04-062-9/+6
| | | | | | | | | | | | | | | | | Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PL111LcdArmVExpressLib: fix incorrect FreePool () callArd Biesheuvel2017-04-061-1/+1
| | | | | | | | | | | | | | When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/HdLcdArmVExpressLib: fix incorrect FreePool () callArd Biesheuvel2017-04-061-1/+1
| | | | | | | | | | | | | | When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/FVP: map motherboard VRAM as uncached memoryArd Biesheuvel2017-04-062-7/+18
| | | | | | | | | | | | | | | | | | The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoDxe: simplify ACPI table installationArd Biesheuvel2017-04-051-36/+1
| | | | | | | | | | | Having a three way conditional with callbacks would make sense if the callbacks weren't (a) identical and (b) didn't return TRUE all the time. So get rid of the kludge. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoPkg: remove PCI host bridge driverArd Biesheuvel2017-04-057-2270/+0
| | | | | | | | | | | | | | | | We are switching the Juno platform to the generic host bridge driver, which involves implementing PciHostBridgeLib for this platform, and plugging it into MdeModulePkg's PciHostBridgeDxe.inf. Since the platform descriptions no longer live in upstream EDK2, the PciHostBridgeLib implementation (which reuses some of the code removed here) will live there as well. But this PciHostBridgeDxe driver is no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoDxe: don't register OnEndOfDxe event on rev R0Ard Biesheuvel2017-04-051-24/+19
| | | | | | | | | | | | | The ArmJunoDxe driver code registers a callback for the EndOfDxe event, at which time it does some manipulation of the PCI peripherals on the board. Given that R0 has no working PCIe, instead of conditionally performing these operations, omit the registration of the callback altogether on that platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoDxe: use the generic non-discoverable device supportArd Biesheuvel2017-04-056-1190/+27
| | | | | | | | | | | Replace the open coded reimplementation of 'PCI emulation' with a pair of calls into NonDiscoverableDeviceRegistrationLib to register the OHCI and EHCI controllers. These will be picked up by the generic driver instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoDxe: remove BdsLib dependencyArd Biesheuvel2017-04-051-1/+0
| | | | | | | | | | The ArmJunoDxe driver does not actually depend on the deprecated BdsLib so remove the dependency declaration from the INF file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmShellCmdRunAxf: remove BdsLib dependencyArd Biesheuvel2017-04-052-2/+57
| | | | | | | | | | | Remove ArmShellCmdRunAxf's dependency on the deprecated BdsLib by cloning the ShutdownUefiBootServices() routine into a local source file; this is the only BdsLib feature 'runaxf' depends on. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PlatformIntelBdsLib: don't clobber ConSplitter handleArd Biesheuvel2017-03-031-10/+15
| | | | | | | | | | | | | | | | The InitializeConsolePipe() routine takes care to only set its output argument *Interface if it is not already set, to prevent overwriting the ConSplitter interface pointer that may have already been assigned. However, the associated OUT argument 'Handle' is clobbered by the subsequent unnecessary LocateDevicePath() invocation, which should similarly be made dependent on whether *Interface has been set already. Reported-by: "Lee, Terry Ping-Chung" <terry.lee@hpe.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmPlatformStackLib: use callee preserved registersArd Biesheuvel2017-02-221-24/+19
| | | | | | | | | | | | | | | | | | The entry code in ArmPlatformStackSet () is a 1:1 transliteration of the ARM version, which uses the callee preserved registers r3 - r7 (*) to preserve the function arguments and the link register across a call to ArmPlatformIsPrimaryCore (). However, x3 - x7 are not callee preserved on AARCH64, and so we should use registers >= x19 instead. While we're at it, drop an unnecessary preserve of the link register, and simplify/deobfuscate the calculation of the secondary stack position. (*) Note that r3 is not actually a callee saved register even on ARM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PL061Gpio: fix the offset value in Get functionHaojian Zhuang2017-02-161-1/+1
| | | | | | | | | When call PL061GetPins() or PL061SetPins(), should use GPIO_PIN_MASK(offset) as parameter, not offset. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PL061: remove duplicated PL061_GPIO_DATA_REGHaojian Zhuang2017-02-161-4/+4
| | | | | | | | | | PL061_GPIO_DATA_REG offset is referenced in PL061EffectiveAddress () already. So remove the duplicated reference when invoke PL061GetPins () or PL061SetPins (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/TZASC: Allow specifying subregions to be disabledBhupesh Sharma2017-01-263-11/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM TZASC-380 IP provides a mechanism to split memory regions being protected via it into eight equal-sized sub-regions. A bit-setting allows the corresponding subregion to be disabled. Several NXP/FSL SoCs support the TZASC-380 IP block and allow the DDR connected via the TZASC to be partitioned into regions having different security settings and also allow subregions to be disabled. This patch enables this support and can be used for SoCs which support such a partition of DDR regions. Details of the 'subregion_disable' register can be viewed here: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0431c/CHDIGDCI.html Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@nxp.com> [bhupesh.linux@gmail.com : Added gmail ID as NXP one is no longer valid] Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe: Fixed crash on Juno R0Daniil Egranov2017-01-251-2/+9
| | | | | | | | | | The Marvell Yukon MAC address load supported only on Juno R1 and R2. It disabled for Juno R0 due to PCI issues on this board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: Change Flash memory attributes before writesAchin Gupta2017-01-201-22/+23
| | | | | | | | | | | | | | | In NorFlashFvbInitialize() if a valid Firmware Volume header is not found at the start of NOR Flash, the Flash memory is written before it has been remapped with EFI_MEMORY_UC attributes to allow write commands. Since the flash memory was previously mapped with Normal and possibly cacheable memory attributes, the Flash commands might never reach the device. This patch fixes this issue by remapping the Flash memory region with correct memory attributes before writing to it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Achin Gupta <achin.gupta@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: Use EfiEventGroupSignal from UefiLibStar Zeng2017-01-203-36/+6
| | | | | | | | | | | | | | | Use EfiEventGroupSignal from UefiLib and remove EmptyCallbackFunction. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=298 Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/ArmJunoDxe: Set Marvell Yukon MAC addressDaniil Egranov2017-01-102-0/+302
| | | | | | | | | The patch reads a valid MAC address from the Juno IOFPGA registers and pushes it into onboard Marvell Yukon NIC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Fix VE RTSM mem map descriptor countSami Mujawar2016-11-251-2/+3
| | | | | | | | | | | | | | | The number of memory map entries used exceeded the allocated count, thereby causing memory corruption. Fixed the number of Virtual Memory Map Descriptors allocated in describing the RTSM Memory Map. Also added an assert to confirm that the descriptor count has not been exceeded, in the hope that it may help highlight the problem should a new entry be added. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg: Reformat VE Memory Map codeEvan Lloyd2016-11-251-54/+45
| | | | | | | | | | | | | | | This change is purely cosmetic, with no functional impact, and only exists to isolate cosmetic changes from a functional fix. Some indentation is adjusted. Overlength lines are re-flowed. alignment on = is adjusted as some lines exceeded 80 columns. if statement converted to conditional assignment. Redundant re-calculation of CacheAttributes removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/PL180MciDxe: update for identifying SDHaojian Zhuang2016-11-241-7/+22
| | | | | | | | | | | When CMD6 & ACMD51 are added into identifying SD process, PL180 should also support CMD6 & ACMD51. Otherwise, it will hang when system tries to read expected data. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg/ArmVExpressFastBootDxe: eliminate deprecated string functionsArd Biesheuvel2016-10-281-4/+5
| | | | | | | | | | Get rid of functions that are no longer available when defining DISABLE_NEW_DEPRECATED_INTERFACES Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmVExpressFastBootDxe: clean up code and commentsArd Biesheuvel2016-10-281-5/+74
| | | | | | | | | | | | | | This module contains an implementation of the Android Fastboot Platform protocol. So follow common Tianocore practice, and duplicate the per-method comment blocks from the interface definition into the implementation. In addition, let's make all methods and the procotol struct STATIC, given that they are never referenced via external linkage. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com>
* ArmPlatformPkg/PrePi RVCT: use relative reference to mSystemMemoryEndArd Biesheuvel2016-10-281-1/+1
| | | | | | | | | | Bring the RVCT version of the PrePi entry point code in line with the GCC version, by using a relative rather than an absolute reference to the mSystemMemoryEnd variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/BootMonFs: eliminate deprecated string functionsArd Biesheuvel2016-10-283-14/+16
| | | | | | | | | | Get rid of functions that are no longer available when defining DISABLE_NEW_DEPRECATED_INTERFACES Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: remove ARM BDSArd Biesheuvel2016-10-268-4129/+0
| | | | | | | | | | | This is no longer used, and does not belong in a reference code base, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg/NorFlashDxe: eliminate void pointer arithmeticArd Biesheuvel2016-10-241-1/+1
| | | | | | | | | | | | | | | | | | While most compilers happily allow arithmetic on void pointer, the RVCT compiler does not, and throws the following warning for NorFlashDxe: ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c(894,48) : error #1254-D: arithmetic on pointer to void or function type Since the expression in question involves a cast from UINTN to VOID*, simply add some parentheses to eliminate this warning. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/PrePi: avoid global variable write to mSystemMemoryEndArd Biesheuvel2016-10-244-44/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The global variable mSystemMemoryEnd is initialized by PrePi only if it has not been initialized by ArmPlatformPeiBootAction(). This allows platforms executing under, e.g., ARM Trusted Firmware to dynamically reserve a window at the top of memory that will be used by the secure firmware. However, PrePi is a SEC module, and writing to a global variable violates the SEC constraints, since SEC and PEI may execute from NOR flash. So instead, initialize mSystemMemoryEnd statically. This will ensure it holds the correct value for all implementations where the value is not overridden, but still allows it to be overridden during the call to ArmPlatformPeiBootAction(). Note that this patch also fixes a latent bug on 32-bit platforms where a value of mSystemMemoryEnd exceeding 4 GB would be truncated to 32-bits rather than limited to (4 GB - 1) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmVExpressPkg: add missing '0x' prefix to hex valueSudeep Holla2016-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | Interestingly the build used to succeed even with missing leading '0x' prefix for a hex value before the commit 0613ccbd1357 ("CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit") With the above commit, luckily we get ... raise BadExpression(ERR_ARRAY_ELE % self._Token) BadExpression: This must be HEX value for NList or Array: [e6]. This patch fixes the above error by adding the missing '0x' prefix to the hex value. Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Leif Lindholm <leif.lindholm@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/ArmShellCmdRunAxf: Reference MdePkg protocol definitionRuiyu Ni2016-10-191-4/+2
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe: Fix for PCI Dual Address ↵Daniil Egranov2016-10-121-3/+6
| | | | | | | | | | | | Cycle The fix handles the PCI Dual Address Cycle Attribute case. It allows drivers using PCI DAC run on Juno. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov <daniil.egranov@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPlatformPkg: Remove UINTN cast when setting BaudRate.Alexei2016-10-111-1/+1
| | | | | | | | | | | | | | | SerialPortInitialize() set the BaudRate variable (type UINT64) as: BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate); This commit fixes a potential problem on ARM 32-bit builds, where the UINTN type is defined as UINT32, by removing the cast: BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate); Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Correct mendacious comments.Alexei2016-10-113-16/+11
| | | | | | | | | | | Correct some obviously incorrect comments that have invalid details for the returned values. (Copy /Paste problem?) There are no functional changes in this commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: Fix PL011 FIFO size testEvan Lloyd2016-10-111-5/+6
| | | | | | | | | | | | | This change updates PL011UartInitializePort to compare ReceiveFifoDepth with the correct hardware FIFO size instead of the constant 32 used previously. This corrects a minor bug where a request for a fifo size > 15 and < 32 would not have been honoured on a system with a 16 byte FIFO. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg/NorFlashDxe: use strictly aligned CopyMem()Ard Biesheuvel2016-09-091-2/+61
| | | | | | | | | | | | | | | | | | | The UEFI spec stipulates that unaligned accesses should be enabled on CPUs that support them, which means all of them, given that we no longer support pre-v7 ARM cores, and the AARCH64 bindings mandate support for unaligned accesses unconditionally. This means that one should not assume that CopyMem () is safe to call on regions that may be mapped using device attributes, which is the case for the NOR flash. Since we have no control over the mappings when running under the OS, and given that write accesses require device mappings, we should not call CopyMem () in the read path either, but use our own implementation that is guaranteed to take alignment into account. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPlatformPkg: remove EFI_MEMORY_UC attribute from normal memoryArd Biesheuvel2016-09-083-3/+0
| | | | | | | | | | | | | | | | On ARM systems, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Similarly, DC ZVA instructions are only supported on normal memory, not device memory. So remove the EFI_MEMORY_UC attribute that we set by default on system RAM. If any region requires this attribute, it is up to the driver to set this attribute, and to ensure that no offending operations are performed on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen2016-09-084-15/+15
| | | | | | | | | | | According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 10:10:42 +0000