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* BaseTools IA32/X64: Use GccBase.lds instead of gcc*-ld-scriptArd Biesheuvel2015-08-031-38/+0
| | | | | | | | | | | | | These scripts all now have the same contents, so we only need to use GccBase.lds. Therefore we can delete gcc-4K-align-ld-script, gcc4.4-ld-script and gcc4.9-ld-script. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18142 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools IA32/X64: get header size and alignment from ld commandlineArd Biesheuvel2015-08-031-5/+5
| | | | | | | | | | | | | | Instead of hardcoding the values for the PE/COFF header size and the section alignment, set them on the linker command line. This factors out these values from the various linker scripts, which will allow us to unify them in a subsequent patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18134 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools IA32/X64: move .got contents to the PE/COFF .text sectionArd Biesheuvel2015-08-031-4/+1
| | | | | | | | | | | | | | | Move the .got contents to the PE/COFF .text section. This should be a no-op, since we typically don't generate position independent code (i.e., using -fPIC). But since the GOT contains variable addresses that are updated at relocation time only, its contents are best kept in .text to prevent them from being overwritten inadvertently. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18133 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools IA32/X64: drop redundant alignment from linker scriptArd Biesheuvel2015-08-031-3/+0
| | | | | | | | | | | | | There is no need to pad out the end of a section of the start of the following section is aligned to the same value. So drop the redundant ALIGN() statements. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18132 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools IA32/X64: move .rodata to PE/COFF .text sectionArd Biesheuvel2015-08-031-1/+1
| | | | | | | | | | | | | | | | The .rodata ELF section contains constant non-executable data that should never be modified by the program itself. Since the risk of inadvertent modification is typically higher than the risk of inadvertent execution, it makes sense to put this data in the R-X .text section rather than in the RW- .data section. So move it there. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18131 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools IA32/X64: remove NOP padding from X86/IA32 GCC linker scriptsArd Biesheuvel2015-08-031-1/+1
| | | | | | | | | | | | | | | | | The NOP padding in the GCC linker scripts ensures that all empty regions in the ELF binary are filled with x86 NOP instructions. There is no upside to doing this: if the CPU ends up executing these instructions, we have little hope of resuming normal execution of the program anyway. And having NOP slides in memory only makes it easier for attackers to launch exploits. So remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18130 6f19259b-4bc3-4df7-8a09-765794883524
* BaseTools: Add GCC49 toolchain; align data sections to 0x40Jordan Justen2014-07-281-0/+44
GCC 4.9 may use 64-byte (0x40) alignment for data sections. Therefore we use a different link script for GCC 4.9. The only difference from the gcc4.4-ld-script is the alignment for data sections. When using the GCC48 toolchain with GCC 4.9, this error would be encountered by GenFw: > GenFw: ERROR 3000: Invalid > Unsupported section alignment. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Yingke Liu <yingke.d.liu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15697 6f19259b-4bc3-4df7-8a09-765794883524