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* CorebootModulePkg: Removing ipf from edk2.chenc22018-08-143-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ma, Maurice <maurice.ma@intel.com>
* CorebootModulePkg/CbSupportDxe: Remove SCI_EN settingBenjamin You2018-06-114-53/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implemenation sets PM1_CNT.SCI_EN bit at ReadyToBoot event. However, this should not be done because this causes OS to skip triggering FADT.SMI_CMD, which leads to the functions implemented in the SMI handler being omitted. This issue was identified by Matt Delco <delco@google.com>. The fix does the following: - The SCI_EN bit setting is removed from CbSupportDxe driver. - Some additional checks are added in CbParseFadtInfo() in CbParseLib.c to output some error message and ASSERT (FALSE) if ALL of the following conditions are met: 1) HARDWARE_REDUCED_ACPI is not set; 2) SMI_CMD field is zero; 3) SCI_EN bit is zero; which indicates the ACPI enabling status is inconsistent: SCI is not enabled but the ACPI table does not provide a means to enable it through FADT->SMI_CMD. This may cause issues in OS. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Matt Delco <delco@google.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Matt Delco <delco@google.com>
* CorebootModulePkg/CbSupportDxe: Remove duplicated IO Space additionBenjamin You2017-11-161-3/+0
| | | | | | | | | | | | | Since UefiCpuPkg's CpuDxe Driver already adds Local Apic's MMIO space to GCD, CorebootModulePkg's CbSupportDxe should not do this again. Doing this again causes error return status from GCD service, and ASSERT (FALSE) with debug build, so the duplicated addition is removed. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* edk2: Move License.txt file to rootMichael D Kinney2017-08-031-25/+0
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=642 Add top level License.txt file with the BSD 2-Clause License that is used by the majority of the EKD II open source project content. Merge copyright statements from the BSD 2-Clause License files in each package directory and remove the duplication License.txt file from package directories. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* CorebootPayloadPkg/CbSupportPei: Fix the memory map issueMaurice Ma2016-11-171-0/+5
| | | | | | | | | | | | | | | When coreboot reports memory range across 1MB, the current code cannot handle it properly. In this case the range should be adjusted to start from 1MB instead since the memory resource below 1MB has been preprocessed by CbSupportPei module. This patch fixed the coreboot + UEFI payload hang issue when running on QEMU due to incorrect memory map. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkgPkg: Expose FindCbTag API from CbParseLibgdong12016-10-272-1/+37
| | | | | | | | | | CbPlatformSupportLib might use FindCbTag() API to parse platform specific information. So expose this API. And add EFIAPI to all functions in CbParseLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Fix memmap issuegdong12016-10-264-111/+135
| | | | | | | | | | Some reserved memory (e.g. CSE reserved memory) might be in the middle of usable physical memory. The current memory map caculation could not handle this case. This patch fixed this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: gdong1 <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Add a library to parse platform specific info.gdong12016-10-267-1/+135
| | | | | | | | | | Update CbSupportPei to consume the new library, so platform could provide platform specific library instance to parse platform specif info. And add a NULL library instance to pass build. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: gdong1 <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootPayloadPkg DSC: Add build option to disable deprecated APIsMaurice Ma2016-10-261-1/+2
| | | | | | | | | | | | | | | Add the following definition in the [BuildOptions] section in package DSC files to disable APIs that are deprecated. As a result replaced PcdSet32 with PcdSet32S accordingly to make the build pass. [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES Cc: Prince Agyeman <prince.agyeman@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/SecCore: Adding NASM files in SecCore moduleMa, Maurice2016-08-033-5/+153
| | | | | | | | | | | | | Ported MASM/GAS assembly files into NASM files and updated the inf file to refer to NASM files. This change has been tested with GCC 4.8 and VS2013 build. Cc: Prince Agyeman <prince.agyeman@intel.com> Cc: Lee Leahy <leroy.p.leahy@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Remove unused PCI non-enumeration driversMaurice Ma2016-05-2732-13442/+0
| | | | | | | | | | | | CorebootPayloadPkg has switched to use the generic PciBus and PciHostBridge driver form MdeModulePkg. As a result, the non-enumeration drivers including PciBusNoEnumerationDxe and PciRootBridgenoEnumerationDxe need to be removed. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/CbSupportDxe: Text only supportLeahy, Leroy P2016-05-231-10/+11
| | | | | | | | | | | | Not all platforms have or support graphics. The ASSERT that the frame buffer HOB is not NULL is fatal for these platforms. Convert this into an if statement and make the related PcdSet* calls c onditional on locating the frame buffer HOB. Change-Id: Ibdc4bf5359571f3ce1555efcaf4657b8e363b2cd Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* CorebootModulePkg: Add video resolution PCD initializationMaurice Ma2016-05-203-1/+25
| | | | | | | | | | | The video console resolution related PCDs are required to be initialized after switching to use the generic BdsDxe driver in MdeModulePkg. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootModulePkg: Convert TAB to white space for CbSupportDxe driverMaurice Ma2016-05-201-71/+71
| | | | | | | | | Convert TAB to white space for CbSupportDxe driver. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootModulePkg: Use PCD for memory type information initializationMaurice Ma2016-05-183-22/+33
| | | | | | | | | | | | CorebootModulePkg currently uses a hardcoded table for memory type initialization. It might need to be adjusted by platform to reduce the memory fragmentation. So changing to use PCDs rather than constant values to facilitate the customization. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Remove PciSioSerialDxe and SerialDxe driverMaurice Ma2016-05-1711-4389/+0
| | | | | | | | | | | CorebootPayloadPkg has been changed to use generic SerialDxe driver from MdeModulePkg. As part of the clean-up, the overridden SerialDxe and PciSioSerialDxe drivers in CorebootModulePkg need to be removed. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
* CorebootPayloadPkg/PlatformBdsLib: Pass more serial parametersLeahy, Leroy P2016-05-103-18/+57
| | | | | | | | | | Pass the serial port baudrate, register stride, input clock rate and ID from coreboot to CorebootPayloadPkg. Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootPayloadPkg/PciBusNoEnumerationDxe: Skip disabled devicesLeahy, Leroy P2016-05-101-0/+9
| | | | | | | | | | Skip non-bridge devices which are not enabled either for memory or I/O access. Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/PciBusNoEnumerationDxe: Remove white spaceLeahy, Leroy P2016-05-101-46/+46
| | | | | | | | | Remove trailing white space from PciEnumeratorSupport.c. Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/BaseSerialPortLib: Set DTR and RTSLeahy, Leroy P2016-05-101-2/+3
| | | | | | | | | | | | | | | Ensure communication between the host and the UEFI system running CorebootPayloadPkg. In cases where the host has flow control enabled and the serial connection is providing the flow control signals, the host will not be able to send data to the UEFI system because DTR and RTS are not present. The host may also discard all output data from the UEFI system because DTR is not present. By setting DTR and RTS in the UART initialization code this case works properly. Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/BaseSerialPortLib16550: Remove white-spaceLeahy, Leroy P2016-05-102-64/+64
| | | | | | | | | Remove trailing white space. Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Add BaseSerialPortLib16550Leahy, Leroy P2016-05-103-0/+1164
| | | | | | | | | | Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision 89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5. Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/SerialDxe: Use PlatformHookLibLeahy, Leroy P2016-05-054-0/+623
| | | | | | | | | | Copy the driver from MdeModulePkg/Universal/SerialDxe. Add PlatformHookLib to the Library section of the .inf file to adjust the PCDs for the UART. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg/PciSioSerialDxe: Use PlatformHookLibLeahy, Leroy P2016-05-057-0/+3766
| | | | | | | | | | Copy the driver from MdeModulePkg/Bus/Pci/PciSioSerialDxe. Add PlatformHookLib to the Library section of the .inf file to adjust the PCDs for the UART. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg: Remove DuetPkg referencesLeahy, Leroy P2016-05-0236-0/+15249
| | | | | | | | | | | | | | | | | Remove the references to DuetPkg. Copy the files from revision ffea0a2ce21e8e9878587de2419959a7bfea4021 of DuetPkg into CorebootModulePkg. The components include: * PciBusNoEnumerationDxe * PciRootBridgeNoEnumerationDxe * SataControllerDxe TEST=Build and run on Galileo Gen2 Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg-CbParseLib: Fix bad reference in CbParseLibLeahy, Leroy P2016-02-261-1/+2
| | | | | | | | | | | | Dereferencing pMemTableSize in debug statement displays bad values when it is set to NULL. Display the actual table size value instead. TEST=Build and run on Galileo Gen2 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg-CbParseLib: Add ACPI table verificationLeahy, Leroy P2016-02-261-0/+9
| | | | | | | | | | | Verify the register address in the FADT. TEST=Build and run on Galileo Gen2 when the FADT was not present. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
* CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTEDScott Duplichan2015-08-181-1/+5
| | | | | | | | | | | | | Remove EFI_RESOURCE_ATTRIBUTE_TESTED when reporting lower 640KB memory so that the coreboot header is not erased before being processed by CbParseMemoryInfo. This change is needed for compatibility with SVN revision 18146. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18234 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Get power management register addresses.Guo Dong2015-07-011-1/+24
| | | | | | | | | | | This patch will get power management event register address and power management GPE enable register address. Add missing code in CbParseLib.c. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17791 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Get power management register addresses.Guo Dong2015-06-253-3/+13
| | | | | | | | | | This patch will get power management event register address and power management GPE enable register address. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17714 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbSupportPei: Relace tabs with whitespacesMaurice Ma2015-06-031-177/+177
| | | | | | | | | | | Replace tabs with whitespaces and remove the trailing whitespaces at the end of lines to conform to the coding style. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17551 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbSupportPei: Mask off all legacy 8259 interrupt sourcesMaurice Ma2015-06-033-4/+15
| | | | | | | | | | | | | | | | The current coreboot UEFI payload has an assumption that all interrupt sources should be masked off before transferring control to the payload. However, it is not the case on some platforms, such as QEMU. It will cause boot failure due to unexpected pending interrupt in the payload. To resolve it all legacy 8259 interrupt sources need to be masked piror to the DXE phase. The fix was tested on QEMU virtual platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17550 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Fix GCC build failure.Guo Dong2015-05-272-2/+2
| | | | | | | | | | This patch fixed a GCC build failure issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17519 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbParseLib: Coding style updateGuo Dong2015-05-201-88/+159
| | | | | | | | | | | | | | | This patch update file CbParseLib.c to make it consistent with EDKII coding style: 1) Add function comments. 2) Add {} for if statement. 3) Compare with NULL for pointer and compare with 0 for integer instead of using them like a BOOLEAN. 4) For debug information only, use EFI_D_INFO instead of EFI_D_ERROR 5) Correct IN, OUT modifier Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17487 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbParseLib: Fix coding issue in ACPIGuo Dong2015-05-201-3/+3
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17486 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbParseLib: Remove tab and spacesGuo Dong2015-05-201-247/+245
| | | | | | | | | | Replace tab with space. Remove the sapce at the end of lines. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17485 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbParseLib: Support current Coreboot IMDGuo Dong2015-05-202-15/+58
| | | | | | | | | | The latest coreboot use IMD (In Memory Database) to report Tables. This patch adds IMD support in UEFI payload. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17484 6f19259b-4bc3-4df7-8a09-765794883524
* Coreboot*Pkg/Contributions.txt: Update example email addressJordan Justen2015-04-141-2/+2
| | | | | | | | | | | | | | | Use the example.com domain as recommended in RFC 2606. This was changed for the other EDK II packages in r16724. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17169 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg/CbSupportDxe: Add EFIAPI to CbDxeEntryPointScott Duplichan2015-04-101-0/+1
| | | | | | | | | | | | | All image entry point functions must use EFIAPI. Some GCC toolchains will have a build error without this fix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17154 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: DEBUG print format correctionsScott Duplichan2015-04-103-20/+20
| | | | | | | | | | | Fix DEBUG print formats so that pointers and 64-bit integer values display correctly for both 32-bit and 64-bit builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17153 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Avoid gcc compile fail caused by unrecognized pragmaScott Duplichan2015-04-101-0/+2
| | | | | | | | | | | Prevent gcc from preprocessing Microsofrt specific pragma. Otherwise compile will fail with error: -Werror=unknown-pragma. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17152 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Reformat asm constant to avoid gcc assembler failScott Duplichan2015-04-101-1/+1
| | | | | | | | | | The gnu assembler doesn't allow multiple '$' in an expression. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17146 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Add 'ULL' suffix to avoid gcc 4.4 compile failScott Duplichan2015-04-101-1/+1
| | | | | | | | | | | | Add ULL siffix to 64-bit constants, otherwise gcc44 reports error: integer constant is too large for 'long' type Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Bruce Cran <bruce.cran@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17145 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Change CbParseAcpiTable prototype to avoid gcc failScott Duplichan2015-04-102-3/+3
| | | | | | | | | | | | | | | Use of void** as a generic pointer to pointer is a Microsoft extension to the C language and is not supported by gcc. Without this change, gcc compile fails with error: passing argument 1 of 'CbParseAcpiTable' from incompatible pointer type note: expected 'void **' but argument is of type 'struct EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER **' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17144 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Remove unused static functions to prevent gcc build failScott Duplichan2015-04-101-10/+0
| | | | | | | | | | | The gcc build will fail with -Werror=unused-function when a compilation unit defines a static function but never calls it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17143 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Fix build failure with 32-bit NOOPT targetScott Duplichan2015-04-101-1/+1
| | | | | | | | | | | | Fix build failure with 32-bit NOOPT target by replacing direct shift of 64-bit integer with a function call. Otherwise Microsoft tool chains will generate a call to function __allshl and fail to link. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17142 6f19259b-4bc3-4df7-8a09-765794883524
* CorebootModulePkg: Add EFIAPI to OnReadyToBoot to fix gcc compile failScott Duplichan2015-04-101-2/+3
| | | | | | | | | | | | | Make OnReadyToBoot function match the prototype in UefiLib.h. The change only affects gcc builds because EFIAPI ABI differs from the default ABI when building with gcc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17137 6f19259b-4bc3-4df7-8a09-765794883524
* Pkg-Module: CorebootModulePkgMaurice Ma2015-03-3122-0/+2928
| | | | | | | | | | | | | | | | | | | | | | | | | | Initial coreboot UEFI payload code check in. It provides UEFI services on top of coreboot that allows UEFI OS boot. CorebootModulePkg is the source code package of coreboot support modules that will be used to parse the coreboot tables and report memory/io resources. It supports the following features: - Support Unified Extensible Firmware Interface (UEFI) specification 2.4. - Support Platform Initialization(PI) specification 1.3. - Support execution as a coreboot payload. - Support USB 3.0 - Support SATA/ATA devices. - Support EFI aware OS boot. The following features are not supported currently and have not been validated: - GCC Tool Chains - SMM Execution Environment - Security Boot It was tested on a Intel Bay Trail CRB platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17084 6f19259b-4bc3-4df7-8a09-765794883524
* Pkg-Module: CorebootModulePkgMaurice Ma2015-03-3122-2928/+0
| | | | | | | | | | Reverted the previous check-in since it is at the incorrect directory level. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17083 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 21:34:07 +0000