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* IntelFsp2Pkg: Added changes to enable FPDT performance measurementsYarlagadda, Satya P2016-10-273-10/+28
| | | | | | | | | | | | | | | | | | | | | | IntelFsp2Pkg: 1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the Perf Data from FSP Global data. 2.Replaced the hard coded perf ids to use the standard defines from FspStatuscode.h 3.Add the PerfData form Fsp Global data ( for TempRaminit entry, TempramInit exit, memoryinit entry) to FPDT entries IntelFsp2WrapperPkg: Moved the code to add the FSP FPDT records and wrapper FPDT records from ReadytoBoot event to EndofFirmware event Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Fix typos in commentsGary Lin2016-10-243-5/+5
| | | | | | | | | | | | | | - tempory -> temporary - immediatly -> immediately - permenent -> permanent - funciton -> function Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg/FspSecCore: Make FSP functions position independentMaurice Ma2016-10-121-1/+1
| | | | | | | | | | | | The current AsmGetFspInfoHeader function in FspHeader.nasm is position dependent code since it uses absolute address. Change to use relative address instead to make it position independent. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg/Tools: Add PE32 section rebasing supportMaurice Ma2016-10-051-29/+145
| | | | | | | | | | | | The current SplitFspBin.py can only support TE image format rebasing in an FSP binary. This patch adds PE32 image format rebasing support. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Satya Yarlagadda <Satya.p.yarlagadda@intel.com>
* IntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 PkgsSatya Yarlagadda2016-09-201-4/+7
| | | | | | | | | | | | | | | | | | | Changed the GenCfgOpt.py script to insert pragma pack(1) instead of pragma pack (push, 1) in the upd header files generated during fsp build. This is to align with rest of the EDKII pkgs pragma pack usage. Also, this scripts generates UnusedUpdSpace for UPD address gaps. Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[], thus causing upd space waste to have Natural Alignment. Hence changed the script to use UINT8[] for any unusedUpd fields above 1 byte. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Fix typo and commentsGiri P Mudusuru2016-08-311-17/+17
| | | | | | | | | | Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Add function to get FspInfoHeader before stack is readyYarlagadda, Satya P2016-08-231-2/+9
| | | | | | | | | | | | | | | | we need to locate the FSP Info Header before the stack is initialized to access the cfg region for any UPD. Hence adding the AsmGetFspInfoHeaderNoStack function to support it. Note: This function is there in IntelFspPkg but got removed in IntelFsp2Pkg Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Converted PatchFvUserManual from .docx to .md formatMudusuru, Giri P2016-08-082-0/+123
| | | | | | | | | | | | | | | Converted the the word format of the documentation into markdown format for PatchFv.py V2: updated the commit message descripton Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Converted GenCfgOptUserManual from .docx to .md formatMudusuru, Giri P2016-08-082-0/+353
| | | | | | | | | | | | Converted the the word format of the documentation into markdown format for GenCfgOpt.py Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg DSC: Add build option to disable deprecated APIsHao Wu2016-08-081-0/+3
| | | | | | | | | | | | | Add the following definition in the [BuildOptions] section in package DSC files to disable APIs that are deprecated: [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Only include required header files in FspEas.hMaurice Ma2016-08-051-1/+1
| | | | | | | | | | | | | Current FspEas.h file includes Uefi.h which also refers to lots of other UEFI header files not used by FSP consumer. It caused many unnecessary header file overhead for a bootloader that consumes FSP, such as coreboot. This change reduces the required header file number down to 3. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Locate FSP Info Header dynamicallyYarlagadda, Satya P2016-08-021-9/+8
| | | | | | | | | | | | | | we need to locate the FSP Info Header by calculating offset dynamically to handle the scenario of FSP component is being rebased to different location. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Skip loading Microcode if MicrocodeCodeSize is zeroYarlagadda, Satya P2016-07-271-1/+9
| | | | | | | | | | | | | During asm to Nasm conversion, we missed the code to skip loading the microcode and return success if the size is zero. Added additional check to report error if the microcode size is not zero but less than 2 kB. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Add missing License.txt.Jiewen Yao2016-07-261-0/+25
| | | | | | | | | Add missing License.txt. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Remove CarBase and CarSize from FSP_GLOBAL_DATASatya Yarlagadda2016-07-234-67/+1
| | | | | | | | | | | | | | CarBase and CarSize in Fsp Global data structure are no longer needed as Boot loader doesn't pass them to FSP even in case that BL chooses to skip calling the FspTempRamInit API. In case of FspTempramInit is called, we can use the PCDs to identify the CarBase and Size. Hence we remove the relevant code. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Add missing modules in Package DSCLiming Gao2016-07-201-0/+2
| | | | | | | | | | Package DSC is used to verify the module source build. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg BaseFspPlatformLib: Remove Boot Loader tempram MigrationSatya Yarlagadda2016-07-182-76/+0
| | | | | | | | | | | | | In FSP2.0, Boot loader should migrate its temp ram before calling the tempramexit API to tear down the tempram. so, we don't need the function to migrate the BL TempRam in the IntelFsp2Pkg. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg SecFspSecPlatformLibNull: Remove MASM/GAS filesLiming Gao2016-07-115-334/+1
| | | | | | | | | | Keep NASM file only for new added modules. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg BaseFspSwitchStackLib: Remove MASM/GAS filesLiming Gao2016-07-113-157/+0
| | | | | | | | | | Keep NASM file only for new added modules. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg BaseFspDebugLibSerialPort: Remove MASM/GAS filesLiming Gao2016-07-113-66/+0
| | | | | | | | | | Keep NASM file only for new added modules. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg SecFspSecPlatformLibNull: Convert Ia32/Flat32.asm to NASMLiming Gao2016-06-282-0/+129
| | | | | | | Manually convert Ia32/Flat32.asm to Ia32/Flat32.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg SecFspSecPlatformLibNull: Convert Ia32/SecCarInit.asm to NASMLiming Gao2016-06-281-0/+46
| | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/SecCarInit.asm to Ia32/SecCarInit.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg BaseFspSwitchStackLib: Convert Ia32/Stack.asm to NASMLiming Gao2016-06-282-3/+78
| | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/Stack.asm to Ia32/Stack.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg BaseFspDebugLibSerialPort: Convert Ia32/FspDebug.asm to NASMLiming Gao2016-06-282-3/+35
| | | | | | | | The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert Ia32/FspDebug.asm to Ia32/FspDebug.nasm Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg-BaseFspCommonLib: Add funtion to return the reset required statusYarlagadda, Satya P2016-06-273-0/+41
| | | | | | | | | | | | Added new funtion in FSPCommonLib to update the FSP API return status with the requested return status and return the control to the boot loader. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: rename GetFspVpdDataPointer() to GetFspCfgRegionDataPointer()Jiewen Yao2016-06-182-6/+6
| | | | | | | | | | | | | | | FSP2.0 removed VPD concept. Rename GetFspVpdDataPointer() to GetFspCfgRegionDataPointer() to follow FSP2.0 specification (CfgRegionOffset). Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
* InterFsp2Pkg:Tool: Add user manual for SplitFspBin tool.Jiewen Yao2016-06-161-0/+69
| | | | | | | | | | | | | Besides Split FSP binary, we added some more feature to SplitFspBin tool. Here we add user manual for it to describe all usage. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* IntelFsp2Pkg/Tools: Add FSP rebasing function into SplitFspBin toolMaurice Ma2016-06-011-254/+570
| | | | | | | | | | | | Enhanced the SplitFspBin tool in IntelFsp2Pkg to support: - Rebase FSP 2.0 components to a different base address - Display FSP 2.0 information header Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Add missing OEM status code defines.Giri P Mudusuru2016-06-011-0/+14
| | | | | | | | | | | Adding defines from FSP EAS v2.0 section 11.2.2 Oem Status code. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* IntelFsp2Pkg/Tools: Add BSF bit field support in GenCfgOpt toolMaurice Ma2016-05-271-111/+113
| | | | | | | | | | | | | | The current GenCfgOpt tool does not generate bit fields in BSF. This change will allow bit fields to be created in BSF for a specific FSP UPD item. The argument for the tool is also updated to be in sync with the old usage model in IntelFspPkg. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg/FspApi.h: Add comment for structure definition.Jiewen Yao2016-05-201-0/+33
| | | | | | | | | | | | Add doxygen style comment for structure definition. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* Add IntelFsp2Pkg and IntelFsp2WrapperPkg.Jiewen Yao2016-05-1374-0/+10347
Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
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