summaryrefslogtreecommitdiffstats
path: root/IntelFsp2Pkg
Commit message (Collapse)AuthorAgeFilesLines
* MdePkg: MdeLibs.dsc.inc: Apply StackCheckLibNull to All Module TypesOliver Smith-Denny8 days1-4/+0
| | | | | | | | | | | | | | | Now that the ResetVectors are USER_DEFINED modules, they will not be linked against StackCheckLibNull, which were the only modules causing issues. So, we can now remove the kludge we had before and the requirement for every DSC to include StackCheckLibNull for SEC modules and just apply StackCheckLibNull globally. This also changes every DSC to drop the SEC definition of StackCheckLibNull. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* IntelFsp2Pkg : Refactor BaseFspCommonLib to reduce binary sizeAshraf Ali2024-09-303-30/+43
| | | | | | | | | | | | Moved FspApiReturnStatusReset API to a separate file to eliminate unnecessary inclusion of FspApiReturnStatusReset APIs in driver binary. When the compiler linking the Object files it may not remove all the unused from NASM OBJs. This change is to reorganize the C files to minimize the impact of the NASM behavior resulting is code size reduction. Signed-off-by: Ashraf Ali <ashraf.ali.s@intel.com>
* IntelFsp2Pkg: Add StackCheckLibNullOliver Smith-Denny2024-09-131-0/+4
| | | | | | Adds the null instance of StackCheckLib to SEC modules Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* IntelFsp2Pkg: Support FSP API to save and restore page tableZhiguang Liu2024-09-1111-30/+382
| | | | | | | | | | | | | A potential issue may happen when FSP creates/changes page table while bootloader doesn't expect page table being changed in FSP. Current, FSP API support to save/restore stack, IDT and general purpose registers. Following the same pattern, add save/restore page table support to solve this issue. Note that this feature only impacts FSP API mode, and is controlled by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD default value is set as FALSE. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* IntelFsp2Pkg: Align FSP global data pointer for X64 buildHongbin1 Zhang2024-08-282-9/+9
| | | | | | | | | | | | | When it used 32 bits for set FSP global data pointer under X64 build, it should get FSP global data pointer with 32 bits data under X64 build. Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
* IntelFsp2Pkg: Correcting Data Region Length of MCUD sectionAravind P R2024-08-272-11/+10
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4793 MCUD Data Region Length(DATA_LEN_OF_MCUD) pushed to stack is incorrect for 64-bit. The Data occupied by MCUD section is 32 bytes in 64-bit instead of 16 bytes in 32-bit. This commit inputs the correct the Data Region Length for the MCUD Section and also corrects the code that retrieves this data. Signed-off-by: Aravind P R <aravind.p.r@intel.com>
* IntelFsp2Pkg/PatchFv.py: FIX for GCC 32BIT build errorDuggapu Chinni B2024-05-031-1/+1
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4762 Map file generating 8 byte address offset is not matched with the pattern defined in patchFv tool resulting build error. Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com>
* IntelFsp2Pkg/PatchFv.py: Python 3.12 supportGua Guo2024-04-221-12/+12
| | | | | | | | | | | | | | | Ref to https://docs.python.org/3/whatsnew/3.12.html A backslash-character pair that is not a valid escape sequence now generates Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Python 3.12 supportGua Guo2024-04-221-48/+48
| | | | | | | | | | | | | | | Ref to https://docs.python.org/3/whatsnew/3.12.html A backslash-character pair that is not a valid escape sequence now generates Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* IntelFsp2Pkg: Fsp T new ARCH UPD SupportDuggapu Chinni B2024-04-0914-28/+212
| | | | | | | | | | | | | | | | | | Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Chiu Chasel <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: auto-generate SEC ProcessLibraryConstructorList() declLaszlo Ersek2024-03-083-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Rely on AutoGen for declaring ProcessLibraryConstructorList(). Build-tested with: build -a X64 -b DEBUG -m IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf \ -p IntelFsp2Pkg/IntelFsp2Pkg.dsc -t GCC5 build -a X64 -b DEBUG -m IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf \ -p IntelFsp2Pkg/IntelFsp2Pkg.dsc -t GCC5 Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=990 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240305113843.68812-9-lersek@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* IntelFsp2Pkg\Tools\ConfigEditor:Added new USF config workstream.Arun Sura2024-01-104-55/+602
| | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4638 Config Editor utility addition/changes: Support to enable config editor tool to have a new feature that can load and view the configuration data of compiled VFR or HFR in form of YAML. This can help users to understand and track the configuration data when modifications are made. Requires compiled vfr file as input in YAML format. Running Configuration Editor: python ConfigEditor.py Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Signed-off-by: Arun Sura <arun.surax.soundara.pandian@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/PatchFv: Fix syntax issue in markdown manualRay Ni2023-11-031-19/+19
| | | | | | | | | | | | | | | | | | | | | | According to the markdown language syntax, headings should be after number signs (#). The number of number signs correspond to the heading level. But current PatchFvUserManual.md doesn't insert a space between the number signs and the heading title, resulting the markdown file is not rendered well in markdown viewers. The patch doesn't change any content but only adds spaces to ensure the headings are correctly recognized. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com>
* IntelFsp2Pkg/SwitchStack: Reserve 32B when calling C function in 64bitNi, Ray2023-11-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When FSP runs in API mode, it saves the IDTR in its own stack then switches to bootloader's stack before it returns from FspMemoryInit. Next time when the bootloader calls TempRamExit, FSP switches to its own stack and restores IDTR from its stack saved earlier. However, due to a bug in BaseFspSwitchStackLib, the IDTR saved on FSP's stack might be corrupted that results the following TempRamExit call fails inside FSP due to PeiServices pointer cannot be retrieved from IDT.base - 8. The bug is the assembly code doesn't reserve 32 bytes before calling the C routine in 64bit. According to the x86-64 calling convention, caller is responsible for allocating 32 bytes of "shadow space" on the stack right before calling the function (regardless of the actual number of parameters used). When FSP is built in optimization-off mode, the C routine makes use of the 32-byte "shadow space" which is not reserved by the assembly caller. That causes the IDTR saved on the stack is corrupted by the C routine. The patch fixes so by reserving the 32 bytes before calling C routine. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com>
* IntelFsp2Pkg: CI: Add PrEval entryJoey Vagedes2023-10-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Adds a PrEval entry to the package's ci.yaml file which is used to verify if the package uses a particular library instance when that library instance file (INF) is updated. When a library instance file (INF) is updated, PrEval will review each package's DSC as described in the ci.yaml file to determine if the package uses said library instance. If the package does use the library instance, it will be built and tested to ensure the package is not broken from the change. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Signed-off-by: Joey Vagedes <joeyvagedes@gmail.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add get and set FspSmmInit upd data pointer functionsZhang, Hongbin12023-08-282-0/+63
| | | | | | | | | | | | | | | | | FSP-SMM module need get and set FspSmmInit upd data pointer functions to get and set upd settings. Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Reviewed-by: S Ashraf Ali <ashraf.ali.s@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Support child FV in SplitFspBin.pyKuo, Ted2023-08-281-7/+37
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4502 Update SplitFspBin.py to support child FV in FSP binary. Without the patch, the tool won't be able to rebase the images in child FV in FSP binary. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Cc: Ray Han Lim Ng <ray.han.lim.ng@intel.com> Cc: Susovan Mohapatra <susovan.mohapatra@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/Library/BaseFspCommonLib: Fix OVERRUN Coverity issueRanbir Singh2023-05-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4200 FspData->PerfIdx is getting increased for every call unconditionally in the function SetFspMeasurePoint and hence memory access can happen for out of bound FspData->PerfData[] array entries also. Example - FspData->PerfData is an array of 32 UINT64 entries. Assume a call is made to SetFspMeasurePoint function when the FspData->PerfIdx last value is 31. It gets incremented to 32 at line 400. Any subsequent call to SetFspMeasurePoint functions leads to FspData->PerfData[32] getting accessed which is out of the PerfData array as well as the FSP_GLOBAL_DATA structure boundary. Hence keep array access and index increment inside if block only and return invalid performance timestamp when PerfIdx is invalid. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ranbir Singh <rsingh@ventanamicro.com> Acked-by: Pedro Falcato <pedro.falcato@gmail.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/Tools: Enhance PathFv.py to patch Fd file directlyDuggapu, Chinni B2023-04-182-1/+33
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4412 After shrinking the FSP (FV) component using FMMT, Image size in FSP info header is not in sync with the FV length in FV header. This enhancement helps to patch the FSP image size offset with correct length & can be used to patch any offset directly on the FSP Component Fd. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ted Kuo <ted.kuo@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.Chasel Chiu2023-04-042-43/+48
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391 FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time. Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return directly without parsing rest of the microcode in FV. This patch also removed unnecessary LoadCheck code after supporting CPU microcode already loaded scenario. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.Chasel Chiu2023-04-042-1/+27
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Fix NASM X64 build warnings.Chasel Chiu2023-03-242-11/+9
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4377 Fix below warnings generated by NASM X64 build: /X64/FspHelper.iii:26: warning: signed dword value exceeds bounds /X64/FspHelper.iii:35: warning: signed dword value exceeds bounds /X64/FspApiEntryT.iii:320: warning: dword data exceeds bounds Also replaced "cmp reg, 0" with "test reg, reg" per optimization suggestion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-105-5/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix GCC Compiler warning.S, Ashraf Ali2023-03-101-0/+1
| | | | | | | | | | | | | | | Function definition should match with declaration. [-Wlto-type-mismatch] Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-TKuo, Ted2022-11-115-46/+55
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FSP should support input UPD as NULL.Chasel Chiu2022-11-043-34/+91
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4114 FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead. FSP should not return INVALID_PARAMETER in such cases. In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume. In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Ted Kuo <ted.kuo@intel.com>
* IntelFsp2Pkg: Update Function header to support IA32/X64.Chasel Chiu2022-11-022-8/+8
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4126 Common functions will have either 32bit or 64bit instances which having different return code size. Function header should support both scenarios. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add CI YAML fileMichael Kubacki2022-10-041-0/+90
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 Adds IntelFsp2Pkg to the list of supported build packages for edk2 CI and defines an initial set of CI configuration options. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg/BaseFspMultiPhaseLib: Replace duplicate GUIDMichael Kubacki2022-10-041-1/+1
| | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 The FILE_GUID for this library instance file is a duplicate of Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf. This change replaces the duplicated GUID value with a unique GUID. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg: Fix code formatting errorsMichael Kubacki2022-10-043-9/+10
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4048 This package did not have CI enabled so code changes were merged that fail uncrustify formatting. This change updates those files to include uncustify formatting. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney>
* IntelFsp2Pkg: Fix FspSecCoreI build failure.Chasel Chiu2022-09-152-0/+22
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4049 Link error occurred in certain compiling environment when building FspSecCoreI: unresolved external symbol _TempRamInitApi. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: NvsBufferPtr is missing in Fsp24ApiEntryM.nasmKuo, Ted2022-09-152-2/+4
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4063 Added NvsBufferPtr to FSPM_UPD_COMMON_FSP24 in Fsp24ApiEntryM.nasm to align with FSP 2.4 SPEC. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.Chasel Chiu2022-09-0710-0/+969
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface.Chasel Chiu2022-08-3110-29/+450
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3916 Provide FSP 2.4 MultiPhase interface and scripts support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FSPM_ARCH2_UPD mismatching bug.Chasel Chiu2022-08-152-2/+4
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4019 FSPM_ARCH2_UPD in FspApiEntryM.nasm was not up-to-date and should be fixed for both IA32 and X64 builds. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Fix GenCfgOpt bug for FSPI_UPD support.Chasel Chiu2022-07-291-1/+1
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Fixed a logic bug in GenCfgOpt.py to skip FSPI_UPD when platforms do not support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: FSPI_UPD is not mandatory.Chasel Chiu2022-07-282-26/+31
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 FSPI_UPD is required only When platforms implemented FSP_I component. Updated the scripts to allow FSPI_UPD not present scenario. Also fixed FSP_GLOBAL_DATA structure alignment issue and unnecessary non-backward compatibility change in previous FSP_I patch. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Add FSPI_ARCH_UPD.Chasel Chiu2022-07-224-11/+85
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Adding the missing FSPI_ARCH_UPD, FSP_GLOBAL_DATA_VERSION bumpping up, and some comments for clarification. Also fixed a bug in SplitFspBin.py for FSP-I support. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.Hongbin1 Zhang2022-07-2013-53/+245
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 Add FSP-I API entry point for SMM support. Also update 64bit API entry code to assign ApiIdx to RAX to avoid confusion. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Support 64bit FspResetType for X64 build.Chasel Chiu2022-07-194-36/+41
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3999 FspResetType will be either 32bit or 64 bit basing on the build type. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add Definition of EDKII_PEI_VARIABLE_PPINate DeSimone2022-07-182-1/+202
| | | | | | | | Adds definition of EDKII_PEI_VARIABLE_PPI. Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Update SEC_IDT_TABLE structKuo, Ted2022-07-144-20/+21
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPTOR to have sufficient size reserved in IdtTable for X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling ConventionDuggapu, Chinni B2022-05-312-19/+48
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: cbduggap <chinni.b.duggapu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add FSP 2.3 header supportLoo, Tung Lun2022-05-312-8/+69
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3921 This patch adds a couple of fields supported in FSP 2.3 header from both header generation and tool support perspective. Signed-off-by: Loo Tung Lun <tung.lun.loo@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Add CpuLib to module INFs that depend on UefiCpuLibYu Pu2022-05-062-0/+2
| | | | | | | | | | | | There are two libraries: MdePkg/CpuLib and UefiCpuPkg/UefiCpuLib and UefiCpuPkg/UefiCpuLib will be merged to MdePkg/CpuLib. To avoid build failure, add CpuLib dependency to all modules that depend on UefiCpuLib. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64Ted Kuo2022-04-164-4/+79
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: FspSecCore support for X64Ted Kuo2022-04-1618-19/+1493
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64Ted Kuo2022-04-162-17/+38
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support both IA32 and X64. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64Ted Kuo2022-04-164-24/+252
| | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64. 2.Added FSPx_UPD_COMMON_FSP24 structures. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: X64 compatible changes to support PEI in 64bitTed Kuo2022-04-1610-41/+45
| | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added EFIAPI to FspNotifyPhasePeimEntryPoint, SwapStack and PEI_CORE_ENTRY. 2.Treat both MAX_ADDRESS and MAX_UINT32 as invalid address for FSP global data in FspApiCallingCheck(). 3.Changed AsmReadEsp to AsmReadStackPointer. 4.Changed the type of the return value of AsmReadStackPointer from UINT32 to UINTN. 5.Changed the type of TemporaryMemoryBase, PermenentMemoryBase and BootLoaderStack from UINT32 to UINTN. 6.Some type casting to pointers are UINT32. Changed them to UINTN to accommodate both IA32 and X64. 7.Corrected some typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 13:09:44 +0000