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* FmpDevicePkg: Fix various typosAntoine Cœur2019-07-0918-52/+52
| | | | | | | | Fix one typo in FmpDevicePkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: FSP Python scripts to support 3.x.Chasel Chiu2019-07-013-62/+109
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1930 Updated FSP Python scripts to support both 2.x and 3.x. Test: . Verified with Python 2.7.12 and 3.6.6. . Verified tool result is the same before the change. . Both py -2 and py -3 built binary can boot. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: add TempRamExitPpi.h.Chasel Chiu2019-06-202-4/+63
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1883 Add header file for FSP_TEMP_RAM_EXIT_PPI which is defined by FSP 2.1 spec. Test: Build successfully. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.Chasel Chiu2019-06-112-30/+38
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308 Support rebasing FSP 1.x binary. FSP 1.x has single component in binary so not supported by split command and rebase can be done with the same command for rebasing FSP-T component in FSP 2.x image. Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary can be rebased successfully. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Revert FSP 1.x support.Chasel Chiu2019-05-312-38/+30
| | | | | | | | | | This reverts commit: 591b8cb7f3d026d2fa4483c59f3d5fb14be181bf. Will submit again after freeze done. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg/SplitFspBin.py: Support rebasing 1.x binary.Chasel Chiu2019-05-312-30/+38
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1308 Support rebasing FSP 1.x binary. FSP 1.x has single component in binary so not supported by split command and rebase can be done with the same command for rebasing FSP-T component in FSP 2.x image. Test: both FSP 2.x (Kabylake) and FSP 1.x (BroadwellDE) binary can be rebased successfully. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0967-458/+67
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/BaseFspDebugLibSerialPort: Add new APIsBret Barkelew2019-04-021-5/+98
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1395 Add new APIs' implementation (DebugVPrint, DebugBPrint) in the DebugLib instance. These APIs would expose print routines with VaList parameter and BaseList parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Michael Turner <Michael.Turner@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: FSP can utilize bootloader stackChasel, Chiu2019-01-286-19/+157
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1485 Current FSP utilizes pre-allocated temporary memory from boot loader for both heap and stack. To reduce overall temporary memory usage FSP may share the same stack with boot loader and only needs a smaller memory for heap, no separate memory required for stack. Setting PcdFspHeapSizePercentage to 0 to enable FSP sharing stack with boot loader, in this case boot loader stack has to be large enough for FSP to use. Default is 50 (half memory heap and half memory stack) for backward compatible with original model. Test: Verified on internal platform and booting successfully with both modes. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Add function to get bootloader stack pointerChasel, Chiu2019-01-282-10/+38
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1391 FSP on-going enhancement for stack utilization required to know bootloader stack pointer and this pointer can be retrieved by first input parameter address when FSP-M entry API invoked by bootloader. Test: Verified on internal platform and booting successfully Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Remove unused keyword in new PPI headerChasel, Chiu2019-01-211-1/+0
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1477 There was unused keyword added in FspmArchConfigPpi.h header block and should be removed. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch modeChasel, Chiu2019-01-172-1/+58
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381 In Dispatch mode FSP may consume PPI directly so creating FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD. Also Keeps new structure size 8 bytes alignment as other structures. Test: Verified on internal platform to boot with this PPI installed successfully. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* IntelFsp2Pkg: Fixed potentially NULL pointer accessingChasel, Chiu2018-10-291-2/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1280 When copying IDT table in SecMain, the pointer might be NULL so added the check to fix it. Test: Verified on internal platform and boots successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix GCC49/XCODE build failureChasel, Chiu2018-10-261-3/+2
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1276 Fixed potentially uninitialized variable build failure caused by commit: b1cc6f672f3b924cdb190e5b92db3b47f46a8911 Test: Verified on internal platform and boots successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg: FSP should not override IDTChasel, Chiu2018-10-254-9/+26
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265 FSP should not override IDT table when it is initialized by boot loader. IDT should be re-initialized in FSP only when it is invalid. To mitigate temporary memory usage a PCD PcdFspMaxInterruptSupported created for platform to decide how many interrupts the FSP IDT table can support. Test: Verified on internal platform and boots successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg: Support FSP Dispatch modeChasel, Chiu2018-10-198-67/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241 Add support for both API (original mode) and DISPATCH mode: 1. Add FspMode field from reserved byte of Global Data Structure to tell which mode is selected by boot loader. If boot loader invoking FSP-M API this field will remain as default 0 (API mode), otherwise platform FSP should set this field to 1 (Dispatch mode) when initializing Global Data Structure. 2. gFspInApiModePpiGuid will be instaled when FSP running in API mode and modules only for API mode should have this in depex. 3. If it is DISPATCH mode, FSP will return to PEI dispatcher, not directly return to boot loader. 4. DISPATCH mode supports DXE NotifyPhase drivers so FSP will not wait for PEI NotifyPhase callbacks, instead it will install gFspReadyForNotifyPhasePpiGuid PPI for platform to complete late initialization before transferring to DXE. Test: Verified FSP API and DISPATCH modes on 2 internal platforms and both boot successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support PCD input from command lineChasel, Chiu2018-10-111-1/+16
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231 Build system already support override PCD value by command line so add this support to GenCfgOpt.py Also update revision to 0.53 Test: Verified UPD header files generated can reflect different PCD values from --pcd build command input Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com> Reviewed-by: Zhu Yonghong <yonghong.zhu@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: remove tailing space from output fileChasel, Chiu2018-09-281-2/+9
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212 UPD header files generated by GenCfgOpt.py may have tailing white space from some of the UPD description in DSC, especially when python script automatically switching lines for long description string. This patch will always remove tailing white space for UPD header files. Test: Verified the patch can remove tailing space in output header files when UPD DSC contains intentional tailing white space. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignmentChasel, Chiu2018-09-281-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211 For reducing maintenance effort, the UPD offset can be automatic assigned by GenCfgOpt.py following by alignment requirements. The usage model as below: . If UPD offset in DSC file are all '*', GenCfgOpt.py will assign offset for all UPD automatically. In this case no need to manually hardcode offset to all UPD in DSC. . If UPD offset in DSC file are all not '*', GenCfgOpt.py will use hardcoded offset directly (original usage model) . Tool does not support mixing scenario so UPD offset in DSC should be all '*' or all hardcoded but not mixed. In auto mode UPD offset will be assigned following natural alignment (size aligned) rule and the whole structure size will align to either 32bits or 64bits depends on maximal UPD size in the structure. Test: Verified by both UPD offset hardcoded or '*' in DSC and generated UPD header files are correct. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCDChasel, Chiu2018-09-281-3/+3
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210 FixedAtBuild PCD is suggested to be used instead of FeatureFlag PCD so extend this tool to support. Also skipped PCDs which commented out by '#'. Test: Verified with FixedAtBuild PCD for including or excluding lines in generated UPD header files successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/BaseFspSwitchStackLib: Remove unused PCDsshenglei2018-09-281-4/+0
| | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/BaseFspPlatformLib: Remove unused PCDsshenglei2018-09-281-9/+0
| | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/BaseFspCommonLib: Remove unused PCDsshenglei2018-09-281-5/+0
| | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg/FspSecCore: Remove unused PCDsshenglei2018-09-283-22/+0
| | | | | | | | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812bChasel, Chiu2018-09-287-76/+47
| | | | | | | | | | | | Commit formats had issues so reverted 9 commits from IntelFsp2Pkg and IntelFsp2WrapperPkg. Will re-submit them with correct formats. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* GenCfgOpt.py: remove tailing space from output fileChasel, Chiu2018-09-281-2/+9
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212 UPD header files generated by GenCfgOpt.py may have tailing white space from some of the UPD description in DSC, especially when python script automatically switching lines for long description string. This patch will always remove tailing white space for UPD header files. Test: Verified the patch can remove tailing space in output header files when UPD DSC contains intentional tailing white space. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignmentChasel, Chiu2018-09-281-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211 For reducing maintenance effort, the UPD offset can be automatic assigned by GenCfgOpt.py following by alignment requirements. The usage model as below: . If UPD offset in DSC file are all '*', GenCfgOpt.py will assign offset for all UPD automatically. In this case no need to manually hardcode offset to all UPD in DSC. . If UPD offset in DSC file are all not '*', GenCfgOpt.py will use hardcoded offset directly (original usage model) . Tool does not support mixing scenario so UPD offset in DSC should be all '*' or all hardcoded but not mixed. In auto mode UPD offset will be assigned following natural alignment (size aligned) rule and the whole structure size will align to either 32bits or 64bits depends on maximal UPD size in the structure. Test: Verified by both UPD offset hardcoded or '*' in DSC and generated UPD header files are correct. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCDChasel, Chiu2018-09-281-3/+3
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210 FixedAtBuild PCD is suggested to be used instead of FeatureFlag PCD so extend this tool to support. Also skipped PCDs which commented out by '#'. Test: Verified with FixedAtBuild PCD for including or excluding lines in generated UPD header files successfully. Cc: Jiewen Yao <Jiewen.yao@intel.com> Cc: Gao Liming <liming.gao@intel.com> Cc: Zhu Yonghong <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 04/16] IntelFsp2Pkg/BaseFspSwitchStackLib: Remove unusedChasel, Chiu2018-09-271-4/+0
| | | | | | | | | | | | | | | PCDs The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 03/16] IntelFsp2Pkg/BaseFspPlatformLib: Remove unused PCDsChasel, Chiu2018-09-271-9/+0
| | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 02/16] IntelFsp2Pkg/BaseFspCommonLib: Remove unused PCDsChasel, Chiu2018-09-271-5/+0
| | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* [PATCH v3 01/16] IntelFsp2Pkg/FspSecCore: Remove unused PCDsChasel, Chiu2018-09-273-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | The PCDs below are unused, so they have been removed from inf. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Fix typo in SplitFspBinChasel, Chiu2018-09-211-1/+1
| | | | | | | Signed-off-by: Patrick Georgi <pgeorgi@google.com> Contributed-under: TianoCore Contribution Agreement 1.1 Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* IntelFsp2Pkg: Clean up source filesLiming Gao2018-06-2816-45/+45
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* IntelFsp2Pkg: SplitFspBin.py to support x64 driversChasel, Chiu2018-06-251-12/+70
| | | | | | | | | | | FSP binary potentially can include X64 drivers to simplify implementation or support new features so update SplitFspBin.py to support x64 image headers. Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg-Tools: GenCfgOpt.py shouldn't include specific UPD nameChasel, Chiu2017-11-081-12/+0
| | | | | | | | | | | PcdSerialIoUartDebugEnable UPD is platform specific and should not be included in generic GenCfgOpt.py script. Remove this and platform DSC should control the default value instead. Cc: Jiewen Yao <Jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
* IntelFsp2Pkg: Update Section Name in INF filesLiming Gao2017-10-103-8/+7
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Fix build error with WHOLEARCHIVE optionSong, BinX2017-08-252-0/+22
| | | | | | | | | | Add empty TempRamInitApi function to fix build error with WHOLEARCHIVE option Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* edk2: Move License.txt file to rootMichael D Kinney2017-08-031-25/+0
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=642 Add top level License.txt file with the BSD 2-Clause License that is used by the majority of the EKD II open source project content. Merge copyright statements from the BSD 2-Clause License files in each package directory and remove the duplication License.txt file from package directories. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* IntelFsp2Pkg: Convert files to CRLF line endingHao Wu2017-04-061-7/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Raise exception for invalid BSF optionThomaiyar, Richard Marian2017-03-161-1/+5
| | | | | | | | | | Raise exception for invalid BSF option in GenCfgOpt.py Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Add Readme.mdJiewen Yao2017-03-131-0/+7
| | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
* Make [-D Macros] as optional argument for GenCfgOptedk2-devel On Behalf Of rthomaiy2017-03-011-4/+5
| | | | | | | | | Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: 41d739e breaks flat tree buildZeng, Star2016-12-051-5/+8
| | | | | | | | | | | | | | | | | There may be no environment variable PACKAGES_PATH defined in flat tree, then 41d739e breaks flat tree build. This patch is to update GenCfgOpt.py to be compatible with both flat tree and package path build. Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Tested-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
* IntelFsp2Pkg: Add PACKAGES_PATH supportThomaiyar, Richard Marian2016-11-301-3/+7
| | | | | | | | | | | | Add PACKAGES_PATH support in GenCfgOpt.py Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Use FspSiliconInitDone2 APIThomaiyar, Richard Marian2016-11-241-1/+1
| | | | | | | | | | | | Use FspSiliconInitDone2 API in Notify Phase Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* IntelFsp2Pkg: Support to return error status from FSP API doneThomaiyar, Richard Marian2016-11-142-23/+163
| | | | | | | | | | | | | | | | Added FspMemoryInitDone2, FspTempRamExitDone2, FspSiliconInitDone2 to return error status to Boot Loader for FSP API calls. To maintain backward compatibility existing functions (FspMemoryInitDone, FspTempRamExitDone, FspSiliconInitDone) declaration left untouched. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Removing FSP Data TableSatya Yarlagadda2016-10-282-33/+0
| | | | | | | | | | | | | | | | FSP Base address is part of FSP_INFO_HEADER and we don't need additional table to report the base address of FSP components. we expect Boot loaders to parse the FSP INFO Header to get the base address. Also, this the FSP_DATA_TABLE is not defined in the FSP EAS and we don't see a need for it. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* IntelFsp2Pkg: Added changes to enable FPDT performance measurementsYarlagadda, Satya P2016-10-273-10/+28
| | | | | | | | | | | | | | | | | | | | | | IntelFsp2Pkg: 1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the Perf Data from FSP Global data. 2.Replaced the hard coded perf ids to use the standard defines from FspStatuscode.h 3.Add the PerfData form Fsp Global data ( for TempRaminit entry, TempramInit exit, memoryinit entry) to FPDT entries IntelFsp2WrapperPkg: Moved the code to add the FSP FPDT records and wrapper FPDT records from ReadytoBoot event to EndofFirmware event Cc: Maurice Ma <maurice.ma@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-12 10:59:05 +0000