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* MdePkg: Update DBG2 and SPCR header with NVIDIA 16550 SubtypeAshish Singhal2021-06-012-0/+6
| | | | | | | | | | Add macros for NVIDIA 16550 UART specific debug port subtype in both DBG2 as well as SPCR header file. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
* MdePkg: Add new 16550-compatible Serial Port Subtypes to DBG2Marcin Wojtas2021-06-012-0/+6
| | | | | | | | | | | | | | | The Microsoft Debug Port Table 2 (DBG2) specification revision May 31, 2017 adds support for 16550-compatible Serial Port Subtype with parameters defined in Generic Address Structure (GAS) [1] Reflect that in the EDK2 headers. [1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sunny Wang <sunny.wang@arm.com>
* MdePkg: MmControl: Fix function and structure definition mismatchesKun Qin2021-06-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3397 Current Ppi/MmControl.h file has structure definition of "struct _PEI_MM_CONTROL_PPI". This name mismatches with its definition in PI Specification v1.7 (Errata) as "struct _EFI_PEI_MM_CONTROL_PPI". In addition, field types "PEI_MM_ACTIVATE" and "PEI_MM_DEACTIVATE" used in "struct _PEI_MM_CONTROL_PPI" mismatches with the definition of "EFI_PEI_MM_ACTIVATE" and "EFI_PEI_MM_DEACTIVATE" in the PI spec. This change fixes these mismatches by using the PI spec defined names. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Fixes: 6f33f7a262314af35e2b99c849e08928ea49aa55 Signed-off-by: Kun Qin <kuqin12@gmail.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: add support for RMPADJUST instructionTom Lendacky2021-05-292-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The RMPADJUST instruction will be used by the SEV-SNP guest to modify the RMP permissions for a guest page. See AMD APM volume 3 for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-9-brijesh.singh@amd.com>
* MdePkg/BaseLib: add support for PVALIDATE instructionBrijesh Singh2021-05-292-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The PVALIDATE instruction validates or rescinds validation of a guest page RMP entry. Upon completion, a return code is stored in EAX, rFLAGS bits OF, ZF, AF, PF and SF are set based on this return code. If the instruction completed succesfully, the rFLAGS bit CF indicates if the contents of the RMP entry were changed or not. For more information about the instruction see AMD APM volume 3. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-8-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macros for SNP AP creationTom Lendacky2021-05-291-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces NAE for creating AP when SEV-SNP is enabled in the guest VM. See the GHCB specification, Table 5 "List of Supported Non-Automatic Events" and sections 4.1.9 and 4.3.2, for further details. While at it, define the VMSA state save area that is required for creating the AP. The save area format is defined in AMD APM volume 2, Table B-4 (there is a mistake in the table that defines the size of the reserved area at offset 0xc8 as a dword, when it is actually a word). The format of the save area segment registers is further defined in AMD APM volume 2, sections 10 and 15.5. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-7-brijesh.singh@amd.com> [lersek@redhat.com: fix typo in BZ reference]
* MdePkg/Register/Amd: define GHCB macro for the Page State ChangeBrijesh Singh2021-05-292-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 The Page State Change NAE exit will be used by the SEV-SNP guest to request a page state change using the GHCB protocol. See the GHCB spec section 4.1.6 and 2.3.1 for more detail on the structure definitions. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-6-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macro for Register GPA structureBrijesh Singh2021-05-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 An SEV-SNP guest is required to perform the GHCB GPA registration. See the GHCB specification for further details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-5-brijesh.singh@amd.com>
* MdePkg/Register/Amd: define GHCB macros for hypervisor feature detectionBrijesh Singh2021-05-292-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of GHCB introduces advertisement of features that are supported by the hypervisor. See the GHCB spec section 2.2 for an additional details. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Erdem Aktas <erdemaktas@google.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-4-brijesh.singh@amd.com>
* MdePkg/Register/Amd: realign macros with more space for future expansionBrijesh Singh2021-05-292-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Version 2 of the GHCB spec introduces several new SNP-specific NAEs. Unfortunately, the names for those NAEs break the alignment. Add some white spaces so that the SNP support patches do not break the alignment. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-3-brijesh.singh@amd.com>
* MdePkg/Register/Amd: expand the SEV MSR to include the SNP definitionBrijesh Singh2021-05-291-1/+6
| | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275 Define the SEV-SNP MSR bits. Cc: James Bottomley <jejb@linux.ibm.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
* MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure.Jason2021-04-201-3/+11
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3309 Define new element(Hybird) in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (07h) data structure. Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed: Ray Ni <ray.ni@intel.com>
* MdePkg/Include: Allow CPU specific defines to be predefinedMichael D Kinney2021-04-152-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308 The EDK II Build Specifications do not restrict the set of CPU architectures that can be supported. Remove places in the EDK II that assumes a fixed set of CPU architectures. Update EFI_REMOVABLE_MEDIA_FILE_NAME to allow it to be predefined in tools_def.txt or a DSC file [BuildOptions] section using a *_*_*_CC_FLAGS statement. Add support for the following two defines. If neither are defines, then preserve the current behavior. If either is defined, then compare these 16-bit values to Machine in the EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) and EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) macros. * EFI_IMAGE_MACHINE_TYPE_VALUE * EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Abner Chang <abner.chang@hpe.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* RedfishPkg/RestJsonStructureDxe: Fix typo in function headerAbner Chang2021-04-151-1/+1
| | | | | | | | | | | | In v2, BZ reference is added. BZ#:3030 Fix the typo [in]/[out] of parameter DestroyStructure in function header. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
* MdePkg/BaseLib: Add support for the XSETBV instructionJiaxin Wu2021-04-061-1/+24
| | | | | | | | | | | | | | | | | | | | | | | *v2: refine the coding format. https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include/Protocol: EFI_RESET_NOTIFICATION_PROTOCOL duplicateMichael D Kinney2021-04-011-3/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3286 Remove duplicate declaration of structure type EFI_RESET_NOTIFICATION_PROTOCOL from ResetNotification.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include/Protocol: EFI_HII POPUP_PROTOCOL duplicate declarationMichael D Kinney2021-04-011-3/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3285 Remove duplicate declaration of structure type EFI_HII_POPUP_PROTOCOL from HiiPopup.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add RegisterFilterLib class and NULL instanceDandan Bi2021-03-301-0/+243
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 1. Add a new library class (RegisterFilterLib) to filter and trace port IO/MMIO/MSR access. 2. Add a NULL instance (RegisterFilterLibNull) can be used to keep current behavior. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Abner Chang <abner.chang@hpe.com>
* MdePkg/Include: EFI Redfish Discover protocolAbner Chang2021-03-261-0/+193
| | | | | | | | | | | | | | | Move GUID definition of EFI Redfish Discover protocol to under MdePkg. With this we don't have dependency of RedfishPkg in ShellPkg. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Cc: Peter O'Hanley <peter.ohanley@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Support standalone MM Driver Unload capabilityJiaxin Wu2021-03-181-0/+25
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3240 This patch is to support standalone MM Driver Unload capability by providing _DriverUnloadHandler() function. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Nasm.inc: add macros for C types used in structure definitionRay Ni2021-03-082-2/+78
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: MmUnblockMemoryLib: Added definition and null instanceKun Qin2021-03-051-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3168 This interface provides an abstration layer to allow MM modules to access requested areas that are outside of MMRAM. On MM model that blocks all non-MMRAM accesses, areas requested through this API will be mapped or unblocked for accessibility inside MM environment. For MM modules that need to access regions outside of MMRAMs, the agents that set up these regions are responsible for invoking this API in order for these memory areas to be accessible from inside MM. Example usages: 1. To enable runtime cache feature for variable service, Variable MM module will need to access the allocated runtime buffer. Thus the agent sets up these buffers, VariableSmmRuntimeDxe, will need to invoke this API to make these regions accessible by Variable MM. 2. For TPM ACPI table to communicate to physical presence handler, the corresponding NVS region has to be accessible from inside MM. Once the NVS region are assigned, it needs to be unblocked thourgh this API. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kun Qin <kun.q@outlook.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Message-Id: <MWHPR06MB31028AF0D0785B93E4E7CF63F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
* MdePkg/Include: Add CET instructions to Nasm.incSheng Wei2021-03-022-0/+24
| | | | | | | | | | | | | | | | | | | | This is to add instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP_RAX in Nasm. The open CI is using NASM 2.14.02. CET instructions are supported since NASM 2.15.01. DB-encoded CET instructions need to be removed after open CI update to NASM 2.15.01. The BZ ticket is https://bugzilla.tianocore.org/show_bug.cgi?id=3227 . REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Update IndustryStandard/SmBios.h with processor status dataRebecca Cran2021-02-081-0/+13
| | | | | | | | | Add a bitfield that describes the structure of the byte in the Status field of the SMBIOS Type 4 Processor Information table. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg/Cpuid.h: Change and add some macro definitions.Lou, Yun2021-01-261-5/+14
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 Change and add some macro definitions about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* MdePkg/Tpm2Acpi.h: Add Start Method Specific Parameters for ARM SMCNhi Pham2021-01-251-0/+13
| | | | | | | | | | | Add Start Method Specific Parameters for ARM SMC Start Method described in the TCG ACPI Specification version 1.2, revision 8. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Cpuid.h: Add CPUID_HYBRID_INFORMATION Leaf(1Ah).Jason Lou2021-01-191-1/+62
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 The UefiCpuPkg/CpuCacheInfoLib will reference new definition about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/IndustryStandard: AEST Table definitionMarc Moisson-Franckhauser2021-01-081-0/+357
| | | | | | | | | | | | | | Bugzilla: 3049 (https://bugzilla.tianocore.org/show_bug.cgi?id=3049) Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg/Graphics: Fix spelling mistakesSamer El-Haj-Mahmoud2021-01-061-3/+3
| | | | | | | | | | | | | | Fix various spelling mistakes in GraphicsConsoleDxe, ConsPlitter, and SimpleTextOut header Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ard Biesheuvel <Ard.Biesheuvel@arm.com> Cc: Pete Batard <pete@akeo.ie> Signed-off-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Define structures for Resizable BAR CapabilityLuo, Heng2021-01-041-5/+25
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3138 Define structures for Resizable BAR Capability in MdePkg/Include/IndustryStandard/PciExpress21.h, Change ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c to use new structures. Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/include: Add DMAR SATC Table DefinitionSheng Wei2020-12-151-3/+31
| | | | | | | | | | | | | | | | | | | SoC Integrated Address Translation Cache (SATC) reporting structure is one of the Remapping Structure, which is imported since Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture Specification v3.2. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3109 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Kowalewski Robert <robert.kowalewski@intel.com> Cc: Feng Roger <roger.feng@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE17 field FirmwareVersionRebecca Cran2020-12-101-1/+1
| | | | | | | | "FirmwareVersion" was misspelled "FirwareVersion". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE4 field ProcessorManufacturerRebecca Cran2020-12-101-1/+1
| | | | | | | | | | In SmBios.h, the SMBIOS_TABLE_TYPE4 field "ProcessorManufacture" should be "ProcessorManufacturer". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix typos in SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS structRebecca Cran2020-12-101-11/+11
| | | | | | | | Fix typos of "Processor64BitCapable", "ProcessorEnhancedVirtualization", and Processor128BitCapable. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issuesMichael D Kinney2020-11-171-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3074 * Fix offset of LinkLayerControlAndStatus in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerAckTimerControl in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerDefeature in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Add CXL_11_SIZE_ASSERT() macro to verify the size of a register layout structure at compile time and use it to verify the sizes of the CXL 1.1 register structures. * Add CXL_11_OFFSET_ASSERT() macro to verify the offset of fields in a register layout structure at compiler time and use it to verify the offset of fields in CXL 1.1 register structures. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ashraf Javeed <ashraf.javeed@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ashraf Javeed <ashraf.javeed@intel.com>
* MdePkg: Clean up GHCB field offsets and save areaTom Lendacky2020-11-101-26/+17
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 Use OFFSET_OF () and sizeof () to calculate the GHCB register field offsets instead of hardcoding the values in the GHCB_REGISTER enum. Define only fields that are used per the GHCB specification, which will result in removing some fields and adding others. Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is not used/defined in the GHCB specification and then rename the reserved fields as appropriate. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <5e9245c7600b9b2d55dd7586b8df28b91b75b72b.1604685192.git.thomas.lendacky@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Definitions for Extended Interrupt FlagsSami Mujawar2020-11-031-0/+11
| | | | | | | | | | | Add Interrupt Vector Flag definitions for Extended Interrupt Descriptor, and macros to test the flags. Ref: ACPI specification 6.4.3.6 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Definitions of EFI REST JSON Structure ProtocolAbner Chang2020-11-021-0/+161
| | | | | | | | | | | | | | | | | Add definitions of EFI REST JSON Structure according to UEFI spec 2.8 Section 29.7.3 EFI REST JSON Resource to C Structure Converter. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Fan Wang <fan.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS to be UINT16Rebecca Cran2020-10-301-11/+11
| | | | | | | | | The ProcessorCharacteristics is a UINT16 field, so the PROCESSOR_CHARACTERISTIC_FLAGS bitfield should be UINT16 too. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Update SmBios.h to add SMBIOS 3.4.0 ARM64 SoC ID fieldRebecca Cran2020-10-301-1/+2
| | | | | | | | | | SMBIOS 3.4.0 defines bit 9 of the Type 4 table Processor Characteristics field to be the ARM64 SoC ID support. Add it to the PROCESSOR_CHARACTERISTIC_FLAGS struct bitfield. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SystemResourceTable.h: Add vendor range valuesMichael Kubacki2020-10-281-0/+13
| | | | | | | | | | | | | | | | | Adds the following macros to define the unsuccessful vendor range min and max (defined in UEFI Specification 2.8): 1. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 2. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Fix wrong spelling in http11.hAbner Chang2020-10-281-4/+4
| | | | | | | | | | | | | | | | | BZ #3019, https://bugzilla.tianocore.org/show_bug.cgi?id=3019 Fix wrong spelling of CHUNK_TRNASFER_* in HTTP11.h. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add HTTP definitionsAbner Chang2020-10-161-1/+5
| | | | | | | | | | | | | | | | BZ #2915, https://bugzilla.tianocore.org/show_bug.cgi?id=2915 Add HTTP chunk transfer definitions. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Definitions of EFI REST EX ProtocolAbner Chang2020-10-151-0/+390
| | | | | | | | | | | | | | | | | | | Add definitions of EFI REST EX Protocol according to UEFI spec v2.8 Section 29.7.2 EFI REST EX Protocol. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Fan Wang <fan.wang@intel.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove code wrapped by DISABLE_NEW_DEPRECATED_INTERFACESZhang, Shenglei2020-10-134-1092/+0
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777 Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated. So remove it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UefiSpec: separate page access bitmask from SP and CRYPTO capsMalgorzata Kukiello2020-10-101-1/+2
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2982 Operating systems are capable of treating SP and CRYPTO memory capabilities and not as attributes. This means that these capabilites cannot be hidden from OSs. For this reason, the SP and CRYPTO bits should be separated from the bitmask that we use for hiding the page-access attributes. Common mask for ATTRIBUTES was introduced in 3bd5c994c879f78e8e3d5346dc3b627f199291aa Signed-off-by: Malgorzata Kukiello <jacek.kukiello@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Oleksiy Yakovlev <oleksiyy@ami.com> Cc: Ard Biesheuvel (ARM address) <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".Wang, Sanyo2020-10-101-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352 SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sanyo Wang <sanyo.wang@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* MdePkg: Correct EFI_BLOCK_IO_PROTOCOL_REVISION3 valueMichael Kubacki2020-09-181-1/+1
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2961 The value of EFI_BLOCK_IO_PROTOCOL_REVISION3 is currently 0x00020031. However, the value assigned in the UEFI Specification 2.8B is ((2<<16) | (31)) which is 0x0002001F. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: PciExpressLib support variable size MMCONFMarcello Sylvester Bauer2020-09-161-2/+3
| | | | | | | | | | | | | Add support for arbitrary sized MMCONF by introducing a new PCD. Add a return value to point out invalid PCI addresses. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com> Cc: Patrick Rudolph <patrick.rudolph@9elements.com> Cc: Christian Walter <christian.walter@9elements.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Correcting EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT definitionPaul2020-08-301-1/+1
| | | | | | | | | | | | | In Acpi10.h, EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT is defined as 0x10, but should be 0x02 per the ACPI Specification. REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2937 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paul G <paul.grimes@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 12:37:51 +0000