summaryrefslogtreecommitdiffstats
path: root/MdePkg/Library
Commit message (Collapse)AuthorAgeFilesLines
* MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchainTakuto Naito2021-04-141-4/+3
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325 1. AsmReadMsr64() in X64/GccInlinePriv.c AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead returns False. This causes build error with the CLANG toolchain. 2. AsmWriteMsr64() in X64/GccInlinePriv.c In the case that FilterBeforeMsrWrite changes Value and returns True, The original Value, not the changed Value, is written to the MSR. This behavior is different from the one of AsmWriteMsr64() in X64/WriteMsr64.c for the MSFT toolchain. Signed-off-by: Takuto Naito <naitaku@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Baseib: Filter/trace MSR access for IA32/X64Dandan Bi2021-04-087-43/+129
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/IoLib: Filter/trace port IO/MMIO accessDandan Bi2021-04-089-73/+329
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: Add support for the XSETBV instructionJiaxin Wu2021-04-063-1/+71
| | | | | | | | | | | | | | | | | | | | | | | *v2: refine the coding format. https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add RegisterFilterLib class and NULL instanceDandan Bi2021-03-303-0/+307
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 1. Add a new library class (RegisterFilterLib) to filter and trace port IO/MMIO/MSR access. 2. Add a NULL instance (RegisterFilterLibNull) can be used to keep current behavior. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Abner Chang <abner.chang@hpe.com>
* MdePkg: use CpuPause() in CpuDeadLoop()Ankur Arora2021-03-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CpuPause() might allow the CPU to go into a lower power state state while we spin. On X86, CpuPause() executes a PAUSE instruction which the Intel and AMD specs describe as follows: Intel: "PAUSE: An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor?s power consumption." AMD: "PAUSE: Improves the performance of spin loops, by providing a hint to the processor that the current code is in a spin loop. The processor may use this to optimize power consumption while in the spin loop. Architecturally, this instruction behaves like a NOP instruction." On RISC-V and ARM64, CpuPause() executes a NOP, which is no worse than the tight loop we have. Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Support standalone MM Driver Unload capabilityJiaxin Wu2021-03-182-2/+59
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3240 This patch is to support standalone MM Driver Unload capability by providing _DriverUnloadHandler() function. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UefiLib: Correct the arguments passed to IsLanguageSupported()Chandramohan Akula2021-03-171-2/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3211 Correct the arguments passed to the IsLanguageSupported() function in AddUnicodeString2() and LookupUnicodeString2() as expected by the function Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chandramohan Akula <chandramohan.akula@broadcom.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: MmUnblockMemoryLib: Added definition and null instanceKun Qin2021-03-053-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3168 This interface provides an abstration layer to allow MM modules to access requested areas that are outside of MMRAM. On MM model that blocks all non-MMRAM accesses, areas requested through this API will be mapped or unblocked for accessibility inside MM environment. For MM modules that need to access regions outside of MMRAMs, the agents that set up these regions are responsible for invoking this API in order for these memory areas to be accessible from inside MM. Example usages: 1. To enable runtime cache feature for variable service, Variable MM module will need to access the allocated runtime buffer. Thus the agent sets up these buffers, VariableSmmRuntimeDxe, will need to invoke this API to make these regions accessible by Variable MM. 2. For TPM ACPI table to communicate to physical presence handler, the corresponding NVS region has to be accessible from inside MM. Once the NVS region are assigned, it needs to be unblocked thourgh this API. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kun Qin <kun.q@outlook.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Message-Id: <MWHPR06MB31028AF0D0785B93E4E7CF63F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
* MdePkg: UefiDevicePathLib: Support UefiDevicePathLib under StandaloneMmKun Qin2021-02-016-33/+168
| | | | | | | | | | | | | | This change added an instance of UefiDevicePathLib for StandaloneMm. It abstracts DevicePathFromHandle function into different files for Standalone MM and other instances to avoid linking gBS into MM_STANDALONE drivers. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kun.q@outlook.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SmiHandlerProfileLibNull: Add MM_STANDALONE supportMichael Kubacki2021-02-012-2/+2
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3184 Allows the library instance to be linked with MM_STANDALONE modules. Cc: Eric Dong <eric.dong@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseRngLibDxe: Add DXE_RUNTIME_DRIVER class to RngLibPete Batard2020-11-131-1/+1
| | | | | | | | | | | | | | | The Raspberry Pi platform with Secure Boot enabled currently fails to build with error: Module type [DXE_RUNTIME_DRIVER] is not supported by library instance [/home/appveyor/projects/rpi4/edk2/MdePkg/Library/DxeRngLib/DxeRngLib.inf] Add the missing class to fix this issue. Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseMemoryLibSse2: Take advantage of write combining buffersCompostella, Jeremy2020-10-1610-38/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SSE2 implementation of the ZeroMem(), SetMem(), SetMem16(), SetMem32 and SetMem64 functions is writing 16 bytes per 16 bytes. It hurts the performances so bad that this is even slower than a simple 'rep stos' (4% slower) in regular DRAM. To take full advantages of the 'movntdq' instruction it is better to "queue" a total of 64 bytes in the write combining buffers. This patch implement such a change. Below is a table where I measured (with 'rdtsc') the time to write an entire 100MB RAM buffer. These functions operate almost two times faster. | Function | Arch | Untouched | 64 bytes | Result | |----------+------+-----------+----------+--------| | ZeroMem | Ia32 | 17765947 | 9136062 | 1.945x | | ZeroMem | X64 | 17525170 | 9233391 | 1.898x | | SetMem | Ia32 | 17522291 | 9137272 | 1.918x | | SetMem | X64 | 17949261 | 9176978 | 1.956x | | SetMem16 | Ia32 | 18219673 | 9372062 | 1.944x | | SetMem16 | X64 | 17523331 | 9275184 | 1.889x | | SetMem32 | Ia32 | 18495036 | 9273053 | 1.994x | | SetMem32 | X64 | 17368864 | 9285885 | 1.870x | | SetMem64 | Ia32 | 18564473 | 9241362 | 2.009x | | SetMem64 | X64 | 17506951 | 9280148 | 1.886x | Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix invalid memory access in AArch64 SetJump/LongJumpJan Bobek2020-10-132-8/+8
| | | | | | | | | | | | | | | | | Correct the memory offsets used in REG_ONE/REG_PAIR macros to synchronize them with definition of the BASE_LIBRARY_JUMP_BUFFER structure on AArch64. The REG_ONE macro declares only a single 64-bit register be read/written; however, the subsequent offset is 16 bytes larger, creating an unused memory gap in the middle of the structure and causing SetJump/LongJump functions to read/write 8 bytes of memory past the end of the jump buffer struct. Signed-off-by: Jan Bobek <jbobek@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove code wrapped by DISABLE_NEW_DEPRECATED_INTERFACESZhang, Shenglei2020-10-136-1993/+0
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777 Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated. So remove it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: BaseRngLibDxe: Add RngLib that uses RngDxeMatthew Carlson2020-09-183-0/+252
| | | | | | | | | | | | | | | | This adds a RngLib that uses the RngProtocol to provide randomness. This means that the RngLib is meant to be used with DXE_DRIVERS. Ref: https://github.com/tianocore/edk2/pull/845 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
* MdePkg: TimerRngLib: Added RngLib that uses TimerLibMatthew Carlson2020-09-183-0/+240
| | | | | | | | | | | | | | | | | | Added a new RngLib that provides random numbers from the TimerLib using the performance counter. This is meant to be used for OpenSSL to replicate past behavior. This should not be used in production as a real source of entropy. Ref: https://github.com/tianocore/edk2/pull/845 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
* MdePkg: PciExpressLib support variable size MMCONFMarcello Sylvester Bauer2020-09-166-112/+577
| | | | | | | | | | | | | Add support for arbitrary sized MMCONF by introducing a new PCD. Add a return value to point out invalid PCI addresses. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com> Cc: Patrick Rudolph <patrick.rudolph@9elements.com> Cc: Christian Walter <christian.walter@9elements.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: UefiFileHandleLib: fix buffer overrun in FileHandleReadLine()Vladimir Olovyannikov via groups.io2020-08-241-2/+4
| | | | | | | | | | | | | | | | | If the size of the supplied buffer in FileHandleReadLine(), module UefiFileHandleLib.c, was not 0, but was not enough to fit in the line, the size is increased, and then the Buffer of the new size is zeroed. This size is always larger than the supplied buffer size, causing supplied buffer overrun. Fix the issue by using the supplied buffer size in ZeroMem(). Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Message-Id: <20200702023113.10517-1-vladimir.olovyannikov@broadcom.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> [lersek@redhat.com: remove stray space character from subject line]
* MdePkg: Fix spelling mistake for occurredMichael D Kinney2020-08-191-1/+1
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2361 Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add support for the VMGEXIT instructionTom Lendacky2020-08-163-0/+72
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 VMGEXIT is a new instruction used for Hypervisor/Guest communication when running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE) to occur, resulting in a #VMEXIT with an exit code value of 0x403. Since SEV-ES is only supported in X64, provide the necessary X64 support to execute the VMGEXIT instruction, which is coded as "rep vmmcall". For IA32, since "vmmcall" is not supported in NASM 32-bit mode and VMGEXIT should never be called, provide a stub implementation that is identical to CpuBreakpoint(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib: Add support for the XGETBV instructionTom Lendacky2020-08-163-0/+67
| | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap handler reentry issue.Abner Chang2020-08-121-7/+38
| | | | | | | | | | | | | | | | | | | | | | While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL, this causes the second S-Mode trap is triggered by the machine mode (M-Mode)timer interrupt redirection. The SRET instruction clear Supervisor Previous Privilege (SPP) to zero (User mode) in the second S-Mode interrupt according to the RISC-V spec. Above brings hart to the user mode (U-Mode) when execute SRET in the nested S-Mode interrupt handler because SPP is set to User Mode in the second interrupt. Afterward, system runs in U-Mode and any accesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseMemoryLibOptDxe: Apply BSD-2-Clause-PatentMichael D Kinney2020-08-0611-313/+11
| | | | | | | | | | | | Change license to BSD-2-Clause-Patent using an SPDX-License-Identifier statement. Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* MdePkg/Library/UnitTestHostBaseLib: Add missing servicesMichael D Kinney2020-07-281-0/+34
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2862 Add ReadMmx()/WriteMmx() services Add MemoryFence() service Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseStackCheckLib: Fix PCD type in INFMichael D Kinney2020-07-151-1/+1
| | | | | | | | | | | | | | | | Update INF file to use a [Pcd] section instead of a [FixedPcd] section. [FixedPcd] should only be used in an INF file if the source code looks up the PCD value using the PcdLib FixedPcdGetxx() services. Using [FixedPcd] forces a platform to configure the PCD to type FixedAtBuild. In this case, PcdDebugPropertyMask supports PCD types FixedAtBuild and PatchableInModule. Without this change any platform that wants to use PcdDebugPropertyMask as type PatchableInModule breaks the build. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseLib: Add BaseLib instance for host based unit testsMichael D Kinney2020-07-155-0/+3411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2800 Add a new version of BaseLib that is safe for use from host based unit test applications. Host based unit test applications may need to provide implementations of some BaseLib functions that provide simple emulation to exercise the code under test. The structure UNIT_TEST_HOST_BASE_LIB is filled in with services that provide default emulation for BaseLib APIs that would normally generate exceptions in a host based unit test application. This structure allows an individual unit test to replace the default emulation of a BaseLib service with an alternate version that is required by a specific unit test. A global variable of type UNIT_TEST_HOST_BASE_LIB is provided through the new UnitTestHostBaseLib library class. Normally cmocka would be used to mock services the code under test calls. However, the BaseLib is used by the Unit Test Framework itself, so using a mocked interface is not possible. The use of a structure to provide hooks for unit test is not expected to be a common feature. It should only be required for libraries that are used by both the Unit Test Framework and the code under test where the code under test requires a different behavior than the Unit Test Framework. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Break out IA32/X64 GCC inline privileged functionsMichael D Kinney2020-07-155-2420/+2409
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2800 Break out the IA32/X64 GCC inline functions that can not be used in a unit test host application into their own source file. This does not make any changes to the BaseLib library instance. This is in preparation for a new BaseLib instances that is safe to use with host-based unit test applications. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseCacheMaintenanceLibNull: Add Null instance for host testingMichael D Kinney2020-07-153-0/+266
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2799 The services in CacheMaintenanceLib usually generate exceptions in a unit test host application. Provide a Null instance that can be safely used. This Null instance can also be used as a template for implementing new instances of CacheMaintenanceLib. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseCpuLibNull: Add Null version of CpuLib for host testingMichael D Kinney2020-07-153-0/+74
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2798 The services in CpuLib usually generate exceptions in a unit test host application. Provide a Null instance that can be safely used. This Null instance can also be used as a template for implementing new instances of CpuLib. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/PciSegmentInfoLib: Add missing EFIAPI to GetPciSegmentInfo()Ray Ni2020-06-241-1/+2
| | | | | | | | | | | | All public APIs should have EFIAPI modifier. Somehow PciSegmentInfoLib missed the EFIAPI modifier. The patch updates the library header file and NULL instance in MdePkg to add the missing EFIAPI. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg/BasePrintLib: avoid absolute addresses for error stringsArd Biesheuvel2020-06-161-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mStatusString[] array is constructed as an array of pointer-to-char, which means that on X64 or AARCH64, it is emitted as a single linear list of 64-bit quantities, each containing the absolute address of one of the string literals in memory. This means that each string takes up 8 bytes of additional space, along with 2 bytes of relocation data. It also means that extra work needs to be done at runtime to process these relocations, every time a module is loaded that incorporates this library. So fix both issues, by splitting mStatusString into two arrays of char arrays. The memory footprint decreases from 955 to 843 bytes, and given that in the latter case, the overhead consists of 278 NUL characters rather than 390 bytes worth of absolute addresses and relocation records, the size of a compressed image is reduced even further. For example, when building ArmVirtQemu.dsc in RELEASE mode for AARCH64 with the GCC5 profile, I get: Before FV Space Information FVMAIN [100%Full] 5329920 total, 5329920 used, 0 free FVMAIN_COMPACT [38%Full] 2093056 total, 811840 used, 1281216 free After FV Space Information FVMAIN [100%Full] 5321728 total, 5321728 used, 0 free FVMAIN_COMPACT [38%Full] 2093056 total, 809696 used, 1283360 free So the uncompressed contents of the compressed image are 8 KB smaller, whereas the resulting flash image (consisting of the compressed image along with SEC, PEI_CORE and a set of PEIMs that execute in place) is 2 KB smaller. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Fix SafeString performing assertions on runtime checksVitaly Cheptsov2020-05-221-112/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2054 Runtime checks returned via status return code should not work as assertions to permit parsing not trusted data with SafeString interfaces. Replace ASSERT() with a DEBUG_VERBOSE message. Cc: Andrew Fish <afish@apple.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Brian J. Johnson <brian.johnson@hpe.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Marvin Häuser <mhaeuser@outlook.de> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Vincent Zimmer <vincent.zimmer@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib.Abner Chang2020-05-071-2/+4
| | | | | | | | | | | | | | | | Add RISCV64 arch for BaseSafeIntLib library. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
* MdePkg/BaseSynchronizationLib: RISC-V cache related code.Abner Chang2020-05-072-0/+83
| | | | | | | | | | | | | | | | | Support RISC-V cache related functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseCpuLib: RISC-V Base CPU libraryAbner Chang2020-05-073-3/+27
| | | | | | | | | | | | | | | | | | implementation. Implement RISC-V CPU related functions in BaseCpuLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.Abner Chang2020-05-075-1/+151
| | | | | | | | | | | | | | | | Support RISC-V image relocation. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.cAbner Chang2020-05-072-5/+12
| | | | | | | | | | | | | | | | | | RISC-V MMIO library instance. IoLibArm.c in fact implements a generic Mmio-only (and ANSI C compliant), so rename it to better reflect this. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseCacheMaintenanceLib:Abner Chang2020-05-072-0/+254
| | | | | | | | | | | | | | | | | | | RISC-V cache maintenance implementation. Implement RISC-V cache maintenance functions in BaseCacheMaintenanceLib. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/BaseLib: BaseLib for RISCV64 architectureAbner Chang2020-05-0712-1/+348
| | | | | | | | | | | | | | | | Add RISC-V RV64 BaseLib functions. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
* MdePkg/UefiScsiLib: Set FUA bit for synchronous SCSI Write operationsZurcher, Christopher J2020-04-151-6/+8
| | | | | | | | | | | | | | The FUA (Force Unit Access) bit forces data to be written directly to disk instead of the write cache. This prevents data from being lost if a shutdown or reset is requested immediately after a SCSI write operation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com>
* MdePkg/DxeServicesLib: Add RISC-V architectureDaniel Schaefer2020-04-031-2/+2
| | | | | | | | | | | | | | BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseSafeIntLib: Fix VS20xx IA32 link failuresMichael D Kinney2020-02-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=2525 SafeUint64Mult() looks for 64-bit overflows and performs several 32-bit multiples with 64-bit results to check for all possible overflow conditions. IA32 builds using VS20xx with optimizations enabled are producing a reference to the _allmull intrinsic. The fix is to use MultU64x64() instead of '*' for these operations. These are safe because the inputs are guaranteed to have the upper 32-bits clear, which means MultU64x64() can never overflow with those inputs. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/Smm: Fix various typosAntoine Coeur2020-02-105-29/+29
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-27-philmd@redhat.com>
* MdePkg/Library/Pci: Fix various typosAntoine Coeur2020-02-102-3/+3
| | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-26-philmd@redhat.com>
* MdePkg/Library/Dxe: Fix various typosAntoine Coeur2020-02-109-20/+20
| | | | | | | | | | | | | | Fix various typos in documentation, comments and strings, and remove the duplicated 'the'. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-25-philmd@redhat.com>
* MdePkg: Do not use CreateEventEx unless requiredVitaly Cheptsov via Groups.Io2020-01-1014-47/+15
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2446 There are many firmwares in the wild not supporting CreateEventEx, including devices less than 5 years old. Signed-off-by: Vitaly Cheptsov <vit9696@protonmail.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: Update the comments of IsLanguageSupportedShenglei Zhang2019-11-201-9/+9
| | | | | | | | | | Keep the comment style of IsLanguageSupported align with other functions. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: add null version of RngLibJian J Wang2019-11-143-0/+138
| | | | | | | | | | | | | | | | | | | | | Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 This is null version of RngLib which should be used with modules that inherit an (indirect) dependency on the RngLib class, but never actually call RngLib APIs for consuming randomness. To be more specific, if following components or functionalities are used in a platform, the BaseRngLibNull should *not* be used. Instead, a non-Null version of RngLib must be used (like BaseRngLib for IA32/X64, or future DxeRngLibRngProtocol for all ARCHs). - HddPasswordDxe.inf - AES, TLS (TlsDxe.inf, TlsLib.inf), RSA_OAEP, RSA_PK1 - (If BaseRngLibNull interface ASSERTed at boot time) Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/UefiFileHandleLib: Tolerate more Root handle FileNamesMarvin Haeuser2019-11-041-7/+18
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2295 The current implementation of the FileHandleGetFileName() function assumes that the Root directory always has the FileName '\0'. However, the only requirement the UEFI specification defines is that a prepended '\\' must be supported to access files and folders relative to the Root directory. This patch removes this assumption and supports constructing valid paths for any value of FileName for the Root Directory. In practice, this fixes compatibility issues with File System drivers that report '\\' as the FileName of the Root directory, which currently is both generating an invalid path ("\\\\") and resulting in an EFI_NOT_FOUND result from the CurrentHandle->Open() call. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Marvin Haeuser <mhaeuser@outlook.de> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 21:17:47 +0000