summaryrefslogtreecommitdiffstats
path: root/MdePkg
Commit message (Collapse)AuthorAgeFilesLines
* MdePkg/Include: Allow CPU specific defines to be predefinedMichael D Kinney2021-04-152-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3308 The EDK II Build Specifications do not restrict the set of CPU architectures that can be supported. Remove places in the EDK II that assumes a fixed set of CPU architectures. Update EFI_REMOVABLE_MEDIA_FILE_NAME to allow it to be predefined in tools_def.txt or a DSC file [BuildOptions] section using a *_*_*_CC_FLAGS statement. Add support for the following two defines. If neither are defines, then preserve the current behavior. If either is defined, then compare these 16-bit values to Machine in the EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) and EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) macros. * EFI_IMAGE_MACHINE_TYPE_VALUE * EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Abner Chang <abner.chang@hpe.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* RedfishPkg/RestJsonStructureDxe: Fix typo in function headerAbner Chang2021-04-151-1/+1
| | | | | | | | | | | | In v2, BZ reference is added. BZ#:3030 Fix the typo [in]/[out] of parameter DestroyStructure in function header. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Nickle Wang <nickle.wang@hpe.com>
* MdePkg: Fix AsmReadMsr64() and AsmWriteMsr64() with GCC toolchainTakuto Naito2021-04-141-4/+3
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3325 1. AsmReadMsr64() in X64/GccInlinePriv.c AsmReadMsr64 can return uninitialized value if FilterBeforeMsrRead returns False. This causes build error with the CLANG toolchain. 2. AsmWriteMsr64() in X64/GccInlinePriv.c In the case that FilterBeforeMsrWrite changes Value and returns True, The original Value, not the changed Value, is written to the MSR. This behavior is different from the one of AsmWriteMsr64() in X64/WriteMsr64.c for the MSFT toolchain. Signed-off-by: Takuto Naito <naitaku@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Allow PcdFSBClock to by DynamicAnthony PERARD2021-04-131-4/+4
| | | | | | | | | | | We are going to want to change the value of PcdFSBClock at run time in OvmfXen, so move it to the PcdsDynamic section. Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=2490 Signed-off-by: Anthony PERARD <anthony.perard@citrix.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20210412133003.146438-3-anthony.perard@citrix.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Baseib: Filter/trace MSR access for IA32/X64Dandan Bi2021-04-087-43/+129
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/IoLib: Filter/trace port IO/MMIO accessDandan Bi2021-04-089-73/+329
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg/BaseLib: Add support for the XSETBV instructionJiaxin Wu2021-04-064-2/+95
| | | | | | | | | | | | | | | | | | | | | | | *v2: refine the coding format. https://bugzilla.tianocore.org/show_bug.cgi?id=3284 This patch is to support XSETBV instruction so as to support Extended Control Register(XCR) write. Extended Control Register(XCR) read has already been supported by below commit to support XGETBV instruction: 9b3ca509abd4e45439bbdfe2c2fa8780c950320a Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Cc: Yao Jiewen <jiewen.yao@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include/Protocol: EFI_RESET_NOTIFICATION_PROTOCOL duplicateMichael D Kinney2021-04-011-3/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3286 Remove duplicate declaration of structure type EFI_RESET_NOTIFICATION_PROTOCOL from ResetNotification.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include/Protocol: EFI_HII POPUP_PROTOCOL duplicate declarationMichael D Kinney2021-04-011-3/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3285 Remove duplicate declaration of structure type EFI_HII_POPUP_PROTOCOL from HiiPopup.h. The forward declaration of the top of this file already declared this type. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Consume MdeLibs.dsc.inc for RegisterFilterLibDandan Bi2021-03-311-0/+2
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc was added for some basic/default library instances provided by MdePkg and RegisterFilterLibNull Library was also added into it as the first version of MdeLibs.dsc.inc. So update platform dsc to consume MdeLibs.dsc.inc for RegisterFilterLibNull which will be consumed by IoLib and BaseLib. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg: Add MdeLibs.dsc.inc file to MdePkgDandan Bi2021-03-301-0/+15
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 MdeLibs.dsc.inc is added for some default libraries provided by MdePkg. Platform can include MdeLibs.dsc.inc file to avoid some potential incompatible changes to platform dsc file in future. Only add RegisterFilterLib into it as the first version of MdeLibs.dsc.inc. Can update and maintain MdeLibs.dsc.inc gradually later. "MdeLibs.dsc.inc" for the [LibraryClasses*] section(s) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* MdePkg: Add RegisterFilterLib class and NULL instanceDandan Bi2021-03-306-2/+559
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246 1. Add a new library class (RegisterFilterLib) to filter and trace port IO/MMIO/MSR access. 2. Add a NULL instance (RegisterFilterLibNull) can be used to keep current behavior. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Abner Chang <abner.chang@hpe.com>
* MdePkg/Include: EFI Redfish Discover protocolAbner Chang2021-03-262-1/+197
| | | | | | | | | | | | | | | Move GUID definition of EFI Redfish Discover protocol to under MdePkg. With this we don't have dependency of RedfishPkg in ShellPkg. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Cc: Peter O'Hanley <peter.ohanley@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: use CpuPause() in CpuDeadLoop()Ankur Arora2021-03-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CpuPause() might allow the CPU to go into a lower power state state while we spin. On X86, CpuPause() executes a PAUSE instruction which the Intel and AMD specs describe as follows: Intel: "PAUSE: An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-wait loop greatly reduces the processor?s power consumption." AMD: "PAUSE: Improves the performance of spin loops, by providing a hint to the processor that the current code is in a spin loop. The processor may use this to optimize power consumption while in the spin loop. Architecturally, this instruction behaves like a NOP instruction." On RISC-V and ARM64, CpuPause() executes a NOP, which is no worse than the tight loop we have. Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Ankur Arora <ankur.a.arora@oracle.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Support standalone MM Driver Unload capabilityJiaxin Wu2021-03-183-2/+84
| | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3240 This patch is to support standalone MM Driver Unload capability by providing _DriverUnloadHandler() function. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UefiLib: Correct the arguments passed to IsLanguageSupported()Chandramohan Akula2021-03-171-2/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3211 Correct the arguments passed to the IsLanguageSupported() function in AddUnicodeString2() and LookupUnicodeString2() as expected by the function Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Chandramohan Akula <chandramohan.akula@broadcom.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Nasm.inc: add macros for C types used in structure definitionRay Ni2021-03-082-2/+78
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: MmUnblockMemoryLib: Added definition and null instanceKun Qin2021-03-056-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3168 This interface provides an abstration layer to allow MM modules to access requested areas that are outside of MMRAM. On MM model that blocks all non-MMRAM accesses, areas requested through this API will be mapped or unblocked for accessibility inside MM environment. For MM modules that need to access regions outside of MMRAMs, the agents that set up these regions are responsible for invoking this API in order for these memory areas to be accessible from inside MM. Example usages: 1. To enable runtime cache feature for variable service, Variable MM module will need to access the allocated runtime buffer. Thus the agent sets up these buffers, VariableSmmRuntimeDxe, will need to invoke this API to make these regions accessible by Variable MM. 2. For TPM ACPI table to communicate to physical presence handler, the corresponding NVS region has to be accessible from inside MM. Once the NVS region are assigned, it needs to be unblocked thourgh this API. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Kun Qin <kun.q@outlook.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Message-Id: <MWHPR06MB31028AF0D0785B93E4E7CF63F3969@MWHPR06MB3102.namprd06.prod.outlook.com>
* MdePkg/Include: Add CET instructions to Nasm.incSheng Wei2021-03-022-0/+24
| | | | | | | | | | | | | | | | | | | | This is to add instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP_RAX in Nasm. The open CI is using NASM 2.14.02. CET instructions are supported since NASM 2.15.01. DB-encoded CET instructions need to be removed after open CI update to NASM 2.15.01. The BZ ticket is https://bugzilla.tianocore.org/show_bug.cgi?id=3227 . REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdePkg: Update IndustryStandard/SmBios.h with processor status dataRebecca Cran2021-02-081-0/+13
| | | | | | | | | Add a bitfield that describes the structure of the byte in the Status field of the SMBIOS Type 4 Processor Information table. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Sami Mujawar <sami.mujawar@arm.com>
* MdePkg: UefiDevicePathLib: Support UefiDevicePathLib under StandaloneMmKun Qin2021-02-017-33/+169
| | | | | | | | | | | | | | This change added an instance of UefiDevicePathLib for StandaloneMm. It abstracts DevicePathFromHandle function into different files for Standalone MM and other instances to avoid linking gBS into MM_STANDALONE drivers. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Kun Qin <kun.q@outlook.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SmiHandlerProfileLibNull: Add MM_STANDALONE supportMichael Kubacki2021-02-012-2/+2
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3184 Allows the library instance to be linked with MM_STANDALONE modules. Cc: Eric Dong <eric.dong@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Cpuid.h: Change and add some macro definitions.Lou, Yun2021-01-261-5/+14
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 Change and add some macro definitions about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* MdePkg/Tpm2Acpi.h: Add Start Method Specific Parameters for ARM SMCNhi Pham2021-01-251-0/+13
| | | | | | | | | | | Add Start Method Specific Parameters for ARM SMC Start Method described in the TCG ACPI Specification version 1.2, revision 8. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Cpuid.h: Add CPUID_HYBRID_INFORMATION Leaf(1Ah).Jason Lou2021-01-191-1/+62
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 The UefiCpuPkg/CpuCacheInfoLib will reference new definition about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/IndustryStandard: AEST Table definitionMarc Moisson-Franckhauser2021-01-081-0/+357
| | | | | | | | | | | | | | Bugzilla: 3049 (https://bugzilla.tianocore.org/show_bug.cgi?id=3049) Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg/Graphics: Fix spelling mistakesSamer El-Haj-Mahmoud2021-01-061-3/+3
| | | | | | | | | | | | | | Fix various spelling mistakes in GraphicsConsoleDxe, ConsPlitter, and SimpleTextOut header Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ard Biesheuvel <Ard.Biesheuvel@arm.com> Cc: Pete Batard <pete@akeo.ie> Signed-off-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Define structures for Resizable BAR CapabilityLuo, Heng2021-01-041-5/+25
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3138 Define structures for Resizable BAR Capability in MdePkg/Include/IndustryStandard/PciExpress21.h, Change ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c to use new structures. Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/include: Add DMAR SATC Table DefinitionSheng Wei2020-12-151-3/+31
| | | | | | | | | | | | | | | | | | | SoC Integrated Address Translation Cache (SATC) reporting structure is one of the Remapping Structure, which is imported since Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture Specification v3.2. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3109 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Kowalewski Robert <robert.kowalewski@intel.com> Cc: Feng Roger <roger.feng@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE17 field FirmwareVersionRebecca Cran2020-12-101-1/+1
| | | | | | | | "FirmwareVersion" was misspelled "FirwareVersion". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE4 field ProcessorManufacturerRebecca Cran2020-12-101-1/+1
| | | | | | | | | | In SmBios.h, the SMBIOS_TABLE_TYPE4 field "ProcessorManufacture" should be "ProcessorManufacturer". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix typos in SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS structRebecca Cran2020-12-101-11/+11
| | | | | | | | Fix typos of "Processor64BitCapable", "ProcessorEnhancedVirtualization", and Processor128BitCapable. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issuesMichael D Kinney2020-11-171-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3074 * Fix offset of LinkLayerControlAndStatus in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerAckTimerControl in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerDefeature in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Add CXL_11_SIZE_ASSERT() macro to verify the size of a register layout structure at compile time and use it to verify the sizes of the CXL 1.1 register structures. * Add CXL_11_OFFSET_ASSERT() macro to verify the offset of fields in a register layout structure at compiler time and use it to verify the offset of fields in CXL 1.1 register structures. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ashraf Javeed <ashraf.javeed@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ashraf Javeed <ashraf.javeed@intel.com>
* MdePkg/BaseRngLibDxe: Add DXE_RUNTIME_DRIVER class to RngLibPete Batard2020-11-131-1/+1
| | | | | | | | | | | | | | | The Raspberry Pi platform with Secure Boot enabled currently fails to build with error: Module type [DXE_RUNTIME_DRIVER] is not supported by library instance [/home/appveyor/projects/rpi4/edk2/MdePkg/Library/DxeRngLib/DxeRngLib.inf] Add the missing class to fix this issue. Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add GUID for REST Style FormsetAbner Chang2020-11-111-1/+1
| | | | | | | | | | | | | | | | | BZ: 2916 https://bugzilla.tianocore.org/show_bug.cgi?id=2916 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Signed-off-by: Ye Ting <ting.ye@intel.com> Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Signed-off-by: Wang Fan <fan.wang@intel.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Clean up GHCB field offsets and save areaTom Lendacky2020-11-101-26/+17
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 Use OFFSET_OF () and sizeof () to calculate the GHCB register field offsets instead of hardcoding the values in the GHCB_REGISTER enum. Define only fields that are used per the GHCB specification, which will result in removing some fields and adding others. Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is not used/defined in the GHCB specification and then rename the reserved fields as appropriate. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <5e9245c7600b9b2d55dd7586b8df28b91b75b72b.1604685192.git.thomas.lendacky@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Definitions for Extended Interrupt FlagsSami Mujawar2020-11-031-0/+11
| | | | | | | | | | | Add Interrupt Vector Flag definitions for Extended Interrupt Descriptor, and macros to test the flags. Ref: ACPI specification 6.4.3.6 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Definitions of EFI REST JSON Structure ProtocolAbner Chang2020-11-022-0/+164
| | | | | | | | | | | | | | | | | Add definitions of EFI REST JSON Structure according to UEFI spec 2.8 Section 29.7.3 EFI REST JSON Resource to C Structure Converter. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Fan Wang <fan.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS to be UINT16Rebecca Cran2020-10-301-11/+11
| | | | | | | | | The ProcessorCharacteristics is a UINT16 field, so the PROCESSOR_CHARACTERISTIC_FLAGS bitfield should be UINT16 too. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Update SmBios.h to add SMBIOS 3.4.0 ARM64 SoC ID fieldRebecca Cran2020-10-301-1/+2
| | | | | | | | | | SMBIOS 3.4.0 defines bit 9 of the Type 4 table Processor Characteristics field to be the ARM64 SoC ID support. Add it to the PROCESSOR_CHARACTERISTIC_FLAGS struct bitfield. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SystemResourceTable.h: Add vendor range valuesMichael Kubacki2020-10-281-0/+13
| | | | | | | | | | | | | | | | | Adds the following macros to define the unsuccessful vendor range min and max (defined in UEFI Specification 2.8): 1. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 2. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Fix wrong spelling in http11.hAbner Chang2020-10-281-4/+4
| | | | | | | | | | | | | | | | | BZ #3019, https://bugzilla.tianocore.org/show_bug.cgi?id=3019 Fix wrong spelling of CHUNK_TRNASFER_* in HTTP11.h. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add HTTP definitionsAbner Chang2020-10-161-1/+5
| | | | | | | | | | | | | | | | BZ #2915, https://bugzilla.tianocore.org/show_bug.cgi?id=2915 Add HTTP chunk transfer definitions. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseMemoryLibSse2: Take advantage of write combining buffersCompostella, Jeremy2020-10-1610-38/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SSE2 implementation of the ZeroMem(), SetMem(), SetMem16(), SetMem32 and SetMem64 functions is writing 16 bytes per 16 bytes. It hurts the performances so bad that this is even slower than a simple 'rep stos' (4% slower) in regular DRAM. To take full advantages of the 'movntdq' instruction it is better to "queue" a total of 64 bytes in the write combining buffers. This patch implement such a change. Below is a table where I measured (with 'rdtsc') the time to write an entire 100MB RAM buffer. These functions operate almost two times faster. | Function | Arch | Untouched | 64 bytes | Result | |----------+------+-----------+----------+--------| | ZeroMem | Ia32 | 17765947 | 9136062 | 1.945x | | ZeroMem | X64 | 17525170 | 9233391 | 1.898x | | SetMem | Ia32 | 17522291 | 9137272 | 1.918x | | SetMem | X64 | 17949261 | 9176978 | 1.956x | | SetMem16 | Ia32 | 18219673 | 9372062 | 1.944x | | SetMem16 | X64 | 17523331 | 9275184 | 1.889x | | SetMem32 | Ia32 | 18495036 | 9273053 | 1.994x | | SetMem32 | X64 | 17368864 | 9285885 | 1.870x | | SetMem64 | Ia32 | 18564473 | 9241362 | 2.009x | | SetMem64 | X64 | 17506951 | 9280148 | 1.886x | Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Definitions of EFI REST EX ProtocolAbner Chang2020-10-152-0/+397
| | | | | | | | | | | | | | | | | | | Add definitions of EFI REST EX Protocol according to UEFI spec v2.8 Section 29.7.2 EFI REST EX Protocol. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Fan Wang <fan.wang@intel.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix invalid memory access in AArch64 SetJump/LongJumpJan Bobek2020-10-132-8/+8
| | | | | | | | | | | | | | | | | Correct the memory offsets used in REG_ONE/REG_PAIR macros to synchronize them with definition of the BASE_LIBRARY_JUMP_BUFFER structure on AArch64. The REG_ONE macro declares only a single 64-bit register be read/written; however, the subsequent offset is 16 bytes larger, creating an unused memory gap in the middle of the structure and causing SetJump/LongJump functions to read/write 8 bytes of memory past the end of the jump buffer struct. Signed-off-by: Jan Bobek <jbobek@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove code wrapped by DISABLE_NEW_DEPRECATED_INTERFACESZhang, Shenglei2020-10-1311-3086/+0
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777 Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated. So remove it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UefiSpec: separate page access bitmask from SP and CRYPTO capsMalgorzata Kukiello2020-10-101-1/+2
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2982 Operating systems are capable of treating SP and CRYPTO memory capabilities and not as attributes. This means that these capabilites cannot be hidden from OSs. For this reason, the SP and CRYPTO bits should be separated from the bitmask that we use for hiding the page-access attributes. Common mask for ATTRIBUTES was introduced in 3bd5c994c879f78e8e3d5346dc3b627f199291aa Signed-off-by: Malgorzata Kukiello <jacek.kukiello@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Oleksiy Yakovlev <oleksiyy@ami.com> Cc: Ard Biesheuvel (ARM address) <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".Wang, Sanyo2020-10-101-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352 SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sanyo Wang <sanyo.wang@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* MdePkg: BaseRngLibDxe: Add RngLib that uses RngDxeMatthew Carlson2020-09-184-1/+255
| | | | | | | | | | | | | | | | This adds a RngLib that uses the RngProtocol to provide randomness. This means that the RngLib is meant to be used with DXE_DRIVERS. Ref: https://github.com/tianocore/edk2/pull/845 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 18:54:42 +0000