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* MdePkg/Cpuid.h: Add CPUID_HYBRID_INFORMATION Leaf(1Ah).Jason Lou2021-01-191-1/+62
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3105 The UefiCpuPkg/CpuCacheInfoLib will reference new definition about CPUID_HYBRID_INFORMATION Leaf(1Ah). Signed-off-by: Jason Lou <yun.lou@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdePkg/IndustryStandard: AEST Table definitionMarc Moisson-Franckhauser2021-01-081-0/+357
| | | | | | | | | | | | | | Bugzilla: 3049 (https://bugzilla.tianocore.org/show_bug.cgi?id=3049) Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser <marc.moisson-franckhauser@arm.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdeModulePkg/Graphics: Fix spelling mistakesSamer El-Haj-Mahmoud2021-01-061-3/+3
| | | | | | | | | | | | | | Fix various spelling mistakes in GraphicsConsoleDxe, ConsPlitter, and SimpleTextOut header Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ard Biesheuvel <Ard.Biesheuvel@arm.com> Cc: Pete Batard <pete@akeo.ie> Signed-off-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Define structures for Resizable BAR CapabilityLuo, Heng2021-01-041-5/+25
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3138 Define structures for Resizable BAR Capability in MdePkg/Include/IndustryStandard/PciExpress21.h, Change ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c to use new structures. Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/include: Add DMAR SATC Table DefinitionSheng Wei2020-12-151-3/+31
| | | | | | | | | | | | | | | | | | | SoC Integrated Address Translation Cache (SATC) reporting structure is one of the Remapping Structure, which is imported since Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture Specification v3.2. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3109 Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jenny Huang <jenny.huang@intel.com> Cc: Kowalewski Robert <robert.kowalewski@intel.com> Cc: Feng Roger <roger.feng@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE17 field FirmwareVersionRebecca Cran2020-12-101-1/+1
| | | | | | | | "FirmwareVersion" was misspelled "FirwareVersion". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg,ShellPkg: Fix typo in SMBIOS_TABLE_TYPE4 field ProcessorManufacturerRebecca Cran2020-12-101-1/+1
| | | | | | | | | | In SmBios.h, the SMBIOS_TABLE_TYPE4 field "ProcessorManufacture" should be "ProcessorManufacturer". Also, update SmbiosView PrintInfo.c to use the new field name. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix typos in SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS structRebecca Cran2020-12-101-11/+11
| | | | | | | | Fix typos of "Processor64BitCapable", "ProcessorEnhancedVirtualization", and Processor128BitCapable. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issuesMichael D Kinney2020-11-171-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=3074 * Fix offset of LinkLayerControlAndStatus in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerAckTimerControl in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Fix offset of LinkLayerDefeature in the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure * Add CXL_11_SIZE_ASSERT() macro to verify the size of a register layout structure at compile time and use it to verify the sizes of the CXL 1.1 register structures. * Add CXL_11_OFFSET_ASSERT() macro to verify the offset of fields in a register layout structure at compiler time and use it to verify the offset of fields in CXL 1.1 register structures. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ashraf Javeed <ashraf.javeed@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ashraf Javeed <ashraf.javeed@intel.com>
* MdePkg/BaseRngLibDxe: Add DXE_RUNTIME_DRIVER class to RngLibPete Batard2020-11-131-1/+1
| | | | | | | | | | | | | | | The Raspberry Pi platform with Secure Boot enabled currently fails to build with error: Module type [DXE_RUNTIME_DRIVER] is not supported by library instance [/home/appveyor/projects/rpi4/edk2/MdePkg/Library/DxeRngLib/DxeRngLib.inf] Add the missing class to fix this issue. Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com> Reviewed-by: Andrei Warkentin <awarkentin@vmware.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Add GUID for REST Style FormsetAbner Chang2020-11-111-1/+1
| | | | | | | | | | | | | | | | | BZ: 2916 https://bugzilla.tianocore.org/show_bug.cgi?id=2916 Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com> Signed-off-by: Ye Ting <ting.ye@intel.com> Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Signed-off-by: Wang Fan <fan.wang@intel.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Clean up GHCB field offsets and save areaTom Lendacky2020-11-101-26/+17
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008 Use OFFSET_OF () and sizeof () to calculate the GHCB register field offsets instead of hardcoding the values in the GHCB_REGISTER enum. Define only fields that are used per the GHCB specification, which will result in removing some fields and adding others. Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is not used/defined in the GHCB specification and then rename the reserved fields as appropriate. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <5e9245c7600b9b2d55dd7586b8df28b91b75b72b.1604685192.git.thomas.lendacky@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Definitions for Extended Interrupt FlagsSami Mujawar2020-11-031-0/+11
| | | | | | | | | | | Add Interrupt Vector Flag definitions for Extended Interrupt Descriptor, and macros to test the flags. Ref: ACPI specification 6.4.3.6 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Definitions of EFI REST JSON Structure ProtocolAbner Chang2020-11-022-0/+164
| | | | | | | | | | | | | | | | | Add definitions of EFI REST JSON Structure according to UEFI spec 2.8 Section 29.7.3 EFI REST JSON Resource to C Structure Converter. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Fan Wang <fan.wang@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Fix SmBios.h PROCESSOR_CHARACTERISTIC_FLAGS to be UINT16Rebecca Cran2020-10-301-11/+11
| | | | | | | | | The ProcessorCharacteristics is a UINT16 field, so the PROCESSOR_CHARACTERISTIC_FLAGS bitfield should be UINT16 too. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
* MdePkg: Update SmBios.h to add SMBIOS 3.4.0 ARM64 SoC ID fieldRebecca Cran2020-10-301-1/+2
| | | | | | | | | | SMBIOS 3.4.0 defines bit 9 of the Type 4 table Processor Characteristics field to be the ARM64 SoC ID support. Add it to the PROCESSOR_CHARACTERISTIC_FLAGS struct bitfield. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/SystemResourceTable.h: Add vendor range valuesMichael Kubacki2020-10-281-0/+13
| | | | | | | | | | | | | | | | | Adds the following macros to define the unsuccessful vendor range min and max (defined in UEFI Specification 2.8): 1. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 2. LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Guomin Jiang <guomin.jiang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Wei6 Xu <wei6.xu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include: Fix wrong spelling in http11.hAbner Chang2020-10-281-4/+4
| | | | | | | | | | | | | | | | | BZ #3019, https://bugzilla.tianocore.org/show_bug.cgi?id=3019 Fix wrong spelling of CHUNK_TRNASFER_* in HTTP11.h. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add HTTP definitionsAbner Chang2020-10-161-1/+5
| | | | | | | | | | | | | | | | BZ #2915, https://bugzilla.tianocore.org/show_bug.cgi?id=2915 Add HTTP chunk transfer definitions. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wang Fan <fan.wang@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* BaseMemoryLibSse2: Take advantage of write combining buffersCompostella, Jeremy2020-10-1610-38/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SSE2 implementation of the ZeroMem(), SetMem(), SetMem16(), SetMem32 and SetMem64 functions is writing 16 bytes per 16 bytes. It hurts the performances so bad that this is even slower than a simple 'rep stos' (4% slower) in regular DRAM. To take full advantages of the 'movntdq' instruction it is better to "queue" a total of 64 bytes in the write combining buffers. This patch implement such a change. Below is a table where I measured (with 'rdtsc') the time to write an entire 100MB RAM buffer. These functions operate almost two times faster. | Function | Arch | Untouched | 64 bytes | Result | |----------+------+-----------+----------+--------| | ZeroMem | Ia32 | 17765947 | 9136062 | 1.945x | | ZeroMem | X64 | 17525170 | 9233391 | 1.898x | | SetMem | Ia32 | 17522291 | 9137272 | 1.918x | | SetMem | X64 | 17949261 | 9176978 | 1.956x | | SetMem16 | Ia32 | 18219673 | 9372062 | 1.944x | | SetMem16 | X64 | 17523331 | 9275184 | 1.889x | | SetMem32 | Ia32 | 18495036 | 9273053 | 1.994x | | SetMem32 | X64 | 17368864 | 9285885 | 1.870x | | SetMem64 | Ia32 | 18564473 | 9241362 | 2.009x | | SetMem64 | X64 | 17506951 | 9280148 | 1.886x | Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Definitions of EFI REST EX ProtocolAbner Chang2020-10-152-0/+397
| | | | | | | | | | | | | | | | | | | Add definitions of EFI REST EX Protocol according to UEFI spec v2.8 Section 29.7.2 EFI REST EX Protocol. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Signed-off-by: Fan Wang <fan.wang@intel.com> Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Nickle Wang <nickle.wang@hpe.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/BaseLib: Fix invalid memory access in AArch64 SetJump/LongJumpJan Bobek2020-10-132-8/+8
| | | | | | | | | | | | | | | | | Correct the memory offsets used in REG_ONE/REG_PAIR macros to synchronize them with definition of the BASE_LIBRARY_JUMP_BUFFER structure on AArch64. The REG_ONE macro declares only a single 64-bit register be read/written; however, the subsequent offset is 16 bytes larger, creating an unused memory gap in the middle of the structure and causing SetJump/LongJump functions to read/write 8 bytes of memory past the end of the jump buffer struct. Signed-off-by: Jan Bobek <jbobek@nvidia.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Remove code wrapped by DISABLE_NEW_DEPRECATED_INTERFACESZhang, Shenglei2020-10-1311-3086/+0
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2777 Code wrapped by DISABLE_NEW_DEPRECATED_INTERFACES is deprecated. So remove it. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/UefiSpec: separate page access bitmask from SP and CRYPTO capsMalgorzata Kukiello2020-10-101-1/+2
| | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2982 Operating systems are capable of treating SP and CRYPTO memory capabilities and not as attributes. This means that these capabilites cannot be hidden from OSs. For this reason, the SP and CRYPTO bits should be separated from the bitmask that we use for hiding the page-access attributes. Common mask for ATTRIBUTES was introduced in 3bd5c994c879f78e8e3d5346dc3b627f199291aa Signed-off-by: Malgorzata Kukiello <jacek.kukiello@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Oleksiy Yakovlev <oleksiyy@ami.com> Cc: Ard Biesheuvel (ARM address) <ard.biesheuvel@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: SMBIOS 3.4.0 Update "adding DDR5 definitions".Wang, Sanyo2020-10-101-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2352 SMBIOS 3.4 spec adds new memory device types (DDR5, LPDDR5) Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Sanyo Wang <sanyo.wang@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* MdePkg: BaseRngLibDxe: Add RngLib that uses RngDxeMatthew Carlson2020-09-184-1/+255
| | | | | | | | | | | | | | | | This adds a RngLib that uses the RngProtocol to provide randomness. This means that the RngLib is meant to be used with DXE_DRIVERS. Ref: https://github.com/tianocore/edk2/pull/845 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
* MdePkg: TimerRngLib: Added RngLib that uses TimerLibMatthew Carlson2020-09-184-1/+242
| | | | | | | | | | | | | | | | | | Added a new RngLib that provides random numbers from the TimerLib using the performance counter. This is meant to be used for OpenSSL to replicate past behavior. This should not be used in production as a real source of entropy. Ref: https://github.com/tianocore/edk2/pull/845 Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1871 Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Matthew Carlson <matthewfcarlson@gmail.com>
* MdePkg: Correct EFI_BLOCK_IO_PROTOCOL_REVISION3 valueMichael Kubacki2020-09-181-1/+1
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2961 The value of EFI_BLOCK_IO_PROTOCOL_REVISION3 is currently 0x00020031. However, the value assigned in the UEFI Specification 2.8B is ((2<<16) | (31)) which is 0x0002001F. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
* MdePkg: PciExpressLib support variable size MMCONFMarcello Sylvester Bauer2020-09-168-114/+584
| | | | | | | | | | | | | Add support for arbitrary sized MMCONF by introducing a new PCD. Add a return value to point out invalid PCI addresses. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com> Cc: Patrick Rudolph <patrick.rudolph@9elements.com> Cc: Christian Walter <christian.walter@9elements.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg: Correcting EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT definitionPaul2020-08-301-1/+1
| | | | | | | | | | | | | In Acpi10.h, EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT is defined as 0x10, but should be 0x02 per the ACPI Specification. REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2937 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Paul G <paul.grimes@amd.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdePkg/Include: Add missing definition of SMBIOS type 42h in SmBios.hAbner Chang2020-08-251-0/+9
| | | | | | | | | Add host interface Protocol Type Data Format structure in SmBios.h BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2328 Signed-off-by: Abner Chang <abner.chang@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg: UefiFileHandleLib: fix buffer overrun in FileHandleReadLine()Vladimir Olovyannikov via groups.io2020-08-241-2/+4
| | | | | | | | | | | | | | | | | If the size of the supplied buffer in FileHandleReadLine(), module UefiFileHandleLib.c, was not 0, but was not enough to fit in the line, the size is increased, and then the Buffer of the new size is zeroed. This size is always larger than the supplied buffer size, causing supplied buffer overrun. Fix the issue by using the supplied buffer size in ZeroMem(). Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Message-Id: <20200702023113.10517-1-vladimir.olovyannikov@broadcom.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> [lersek@redhat.com: remove stray space character from subject line]
* MdePkg: Fix spelling mistake for occurredMichael D Kinney2020-08-192-2/+2
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2361 Cc: Liming Gao <liming.gao@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/MdePkg.ci.yaml: Add configuration for Ecc checkShenglei Zhang2020-08-171-0/+12
| | | | | | | | | | Add configuration ExceptionList and IgnoreFiles for package config files. So users can rely on this to ignore some Ecc issues. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseLib: Add support for the VMGEXIT instructionTom Lendacky2020-08-164-0/+86
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 VMGEXIT is a new instruction used for Hypervisor/Guest communication when running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE) to occur, resulting in a #VMEXIT with an exit code value of 0x403. Since SEV-ES is only supported in X64, provide the necessary X64 support to execute the VMGEXIT instruction, which is coded as "rep vmmcall". For IA32, since "vmmcall" is not supported in NASM 32-bit mode and VMGEXIT should never be called, provide a stub implementation that is identical to CpuBreakpoint(). Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/BaseLib: Add support for the XGETBV instructionTom Lendacky2020-08-164-0/+84
| | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Add a structure definition for the GHCBTom Lendacky2020-08-161-0/+166
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 The GHCB is used by an SEV-ES guest for communicating between the guest and the hypervisor. Create the GHCB definition as defined by the GHCB protocol definition. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg: Add the MSR definition for the GHCB registerTom Lendacky2020-08-161-0/+46
| | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 For SEV-ES, the GHCB page address is stored in the GHCB MSR register (0xc0010130). Define the register and the format used for register during GHCB protocol negotiation. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap handler reentry issue.Abner Chang2020-08-121-7/+38
| | | | | | | | | | | | | | | | | | | | | | While RISC-V hart is trapped into S-Mode, the S-Mode interrupt CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled again by RestoreTPL, this causes the second S-Mode trap is triggered by the machine mode (M-Mode)timer interrupt redirection. The SRET instruction clear Supervisor Previous Privilege (SPP) to zero (User mode) in the second S-Mode interrupt according to the RISC-V spec. Above brings hart to the user mode (U-Mode) when execute SRET in the nested S-Mode interrupt handler because SPP is set to User Mode in the second interrupt. Afterward, system runs in U-Mode and any accesses to S-Mode CSR causes the invalid instruction exception. Signed-off-by: Abner Chang <abner.chang@hpe.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Daniel Schaefer <daniel.schaefer@hpe.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Abner Chang <abner.chang@hpe.com> Acked-by: Liming Gao <liming.gao@intel.com>
* MdePkg/BaseMemoryLibOptDxe: Apply BSD-2-Clause-PatentMichael D Kinney2020-08-0611-313/+11
| | | | | | | | | | | | Change license to BSD-2-Clause-Patent using an SPDX-License-Identifier statement. Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* MdePkg/MdePkg.ci.yaml: Add configuration for LicenseCheckShenglei Zhang2020-07-311-0/+4
| | | | | | | | | | | Add configuration IgnoreFiles for package config files. So users can rely on this to skip license conflict for some generated files. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/UnitTestHostBaseLib: Add missing servicesMichael D Kinney2020-07-281-0/+34
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2862 Add ReadMmx()/WriteMmx() services Add MemoryFence() service Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg Base.h: Delete prototype for __builtin_return_addressJessica Clarke2020-07-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1004 Being a compiler builtin, the type of __builtin_return_address is already known to the compiler so no prototype is needed. Clang also errors out when redeclaring certain builtins like this[1], though currently only for ones with custom type checking. At the moment, __builtin_return_address does not use custom type checking and so does not trigger this error, however, the CHERI fork of LLVM, which will form the basis of the toolchain for Arm's experimental Morello platform, does use custom type checking for it, and so gives an error. Thus, simply delete the unnecessary line. [1] llvm/llvm-project@41af97137572ad6d4dafc872e7ecf6bbb08d4984 Cc: Leif Lindholm <leif@nuviainc.com> Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* MdePkg/Include/IndustryStandard: Main CXL headerJaveed, Ashraf2020-07-271-0/+22
| | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Introducing the Cxl.h as the main header file to support all versions of Compute Express Link Specification register definitions. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg/Include/IndustryStandard: CXL 1.1 RegistersJaveed, Ashraf2020-07-272-4/+571
| | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611 Register definitions from chapter 7 of Compute Express Link Specification Revision 1.1 are ported into the new Cxl11.h. The CXL Flex Bus registers are based on the PCIe Extended Capability DVSEC structure header, led to the inclusion of upgraded Pci.h. Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
* MdePkg: Add New Memory AttributesOleksiy Yakovlev2020-07-151-2/+8
| | | | | | | | | | | | | | | Add usage of EFI_MEMORY_SP and EFI_MEMORY_CPU_CRYPTO attributes introduced in UEFI 2.8 (UEFI 2.8, mantis 1919 and 1872) Fix typos in EFI_MEMORY_CPU_CRYPTO description. Add attributes bitmasks, grouped by type. Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Message-Id: <20200702205039.52400-2-oleksiyy@ami.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* MdePkg/Library/BaseStackCheckLib: Fix PCD type in INFMichael D Kinney2020-07-151-1/+1
| | | | | | | | | | | | | | | | Update INF file to use a [Pcd] section instead of a [FixedPcd] section. [FixedPcd] should only be used in an INF file if the source code looks up the PCD value using the PcdLib FixedPcdGetxx() services. Using [FixedPcd] forces a platform to configure the PCD to type FixedAtBuild. In this case, PcdDebugPropertyMask supports PCD types FixedAtBuild and PatchableInModule. Without this change any platform that wants to use PcdDebugPropertyMask as type PatchableInModule breaks the build. Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Add UT_EXPECT_ASSERT_FAILURE() to UnitTestLibMichael D Kinney2020-07-151-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2801 Add the UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) macro to the UnitTestLib that can be used to check if a function under test triggers an ASSERT() condition. If an ASSERT() condition is triggered, then the macro returns. If the ASSERT() condition is not triggered, then the current unit test fails with a status of UNIT_TEST_ERROR_TEST_FAILED. If ASSERT()s are disabled, then this check for ASSERT() behavior is not possible, and the check is skipped. The global variable gUnitTestExpectAssertFailureJumpBuffer is added to the UnitTestLib to save/restore context when the UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) macro is used. The UT_EXPECT_ASSERT_FAILURE() macro uses the SetJump() service with this global variable. The UnitTestLib service UnitTestDebugAssert() uses the LongJump() service with this global to restore context if an ASSERT() is triggered by the code under test. Add UnitTestExpectAssertFailure() to the UnitTestLib class. The UnitTestExpectAssertFailure() is called from the new UT_EXPECT_ASSERT_FAILURE() macro after the status of this macro check is known. Add UnitTestDebugAssert() to the UnitTestLib class. The UnitTestDebugAssert() service is the same as the DebugLib DebugAssert() service and is invoked from the DebugLib _ASSERT() macro if unit testing is enabled. This allows the Unit Test Framework to know when code under test triggers an ASSERT() condition. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Include: Hook DebugLib _ASSERT() for unit testsMichael D Kinney2020-07-151-1/+27
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2801 Update DebugLib.h _ASSERT() macro to check if unit testing is enabled and call UnitTestDebugAssert() instead of DebugAssert() so the an ASSERT() condition that is triggered by a function under test can be handled by the Unit Test Framework. If EDKII_UNIT_TEST_FRAMEWORK_ENABLED is not defined, then the existing DebugLib behavior is preserved. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* MdePkg/Library/BaseLib: Add BaseLib instance for host based unit testsMichael D Kinney2020-07-158-1/+4005
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2800 Add a new version of BaseLib that is safe for use from host based unit test applications. Host based unit test applications may need to provide implementations of some BaseLib functions that provide simple emulation to exercise the code under test. The structure UNIT_TEST_HOST_BASE_LIB is filled in with services that provide default emulation for BaseLib APIs that would normally generate exceptions in a host based unit test application. This structure allows an individual unit test to replace the default emulation of a BaseLib service with an alternate version that is required by a specific unit test. A global variable of type UNIT_TEST_HOST_BASE_LIB is provided through the new UnitTestHostBaseLib library class. Normally cmocka would be used to mock services the code under test calls. However, the BaseLib is used by the Unit Test Framework itself, so using a mocked interface is not possible. The use of a structure to provide hooks for unit test is not expected to be a common feature. It should only be required for libraries that are used by both the Unit Test Framework and the code under test where the code under test requires a different behavior than the Unit Test Framework. Cc: Liming Gao <liming.gao@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Bret Barkelew <Bret.Barkelew@microsoft.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 05:35:46 +0000