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* OvmfPkg/PciHotPlugInitDxe: fix io window sizeGerd Hoffmann2023-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smallest IO window size for PCI bridges is 0x1000. Fix default size accordingly. Avoids broken resource assignments like this: [ ... ] PciBus: Resource Map for Root Bridge PciRoot(0x0) Type = Io16; Base = 0x6000; Length = 0x7000; Alignment = 0xFFF [ ... ] Base = 0xC000; Length = 0x200; Alignment = 0xFFF; Owner = PPB [00|02|00:**] Base = 0xC200; Length = 0x40; Alignment = 0x3F; Owner = PCI [00|1F|03:20] Base = 0xC240; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|1F|02:20] [ ... ] ... which the linux kernel fixes up later: [ 0.644657] pci 0000:00:1f.3: BAR 4: assigned [io 0x1000-0x103f] [ 0.646833] pci 0000:00:1f.2: BAR 4: assigned [io 0x1040-0x105f] With the patch applied: { ... ] PciBus: Resource Map for Root Bridge PciRoot(0x0) Type = Io16; Base = 0x6000; Length = 0x8000; Alignment = 0xFFF [ ... ] Base = 0xC000; Length = 0x1000; Alignment = 0xFFF; Owner = PPB [00|02|00:**] Base = 0xD000; Length = 0x40; Alignment = 0x3F; Owner = PCI [00|1F|03:20] Base = 0xD040; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|1F|02:20] [ ... ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
* OvmfPkg/PciHotPlugInitDxe: Do not reserve IO ports by default.Gerd Hoffmann2023-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Flip the default for IO address space reservations for PCI(e) bridges and root ports with hotplug support from TRUE to FALSE. PCI(e) bridges will still get IO address space assigned in case: (a) Downstream devices actually need IO address space, or (b) Explicit configuration, using "qemu -device pcie-root-port,io-reserve=<size>". In case IO address space is exhausted edk2 will stop assigning resources to PCI(e) bridges. This is not limited to IO resources, the affected bridges will not get any memory resources assigned either. This patch solves this issue by not handing out the scarce IO address space, which is not needed in most cases anyway. Result is a more consistent PCI configuration in virtual machine configurations with many PCie root ports. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* OvmfPkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-04-101-3/+3
| | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout OvmfPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* OvmfPkg/PciHotPlugInitDxe: reserve more mmio spaceGerd Hoffmann2022-10-072-2/+20
| | | | | | | | | | In case the 64-bit pci mmio window is larger than the default size of 32G be generous and hand out larger chunks of address space for prefetchable mmio bridge windows. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: Apply uncrustify changesMichael Kubacki2021-12-071-160/+173
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the OvmfPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
* OvmfPkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()Michael D Kinney2021-12-071-2/+2
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3767 Update use of DEBUG_CODE(Expression) if Expression is a complex code block with if/while/for/case statements that use {}. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Andrew Fish <afish@apple.com>
* OvmfPkg: Change OPTIONAL keyword usage styleMichael D Kinney2021-12-071-1/+1
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Andrew Fish <afish@apple.com>
* OvmfPkg: replace old EFI_D_ debug levels with new DEBUG_ onesRebecca Cran2020-04-301-1/+1
| | | | | | | | | | | | | Generated mechanically with: find OvmfPkg -type f -exec sed -i -e 's/EFI_D_/DEBUG_/g' {} \; Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Cc: Philippe Mathieu-Daude <philmd@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Laszlo Ersek <lersek@redhat.com> Message-Id: <20200429215327.606467-1-rebecca@bsdio.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-092-14/+2
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* OvmfPkg/PciHotPlugInitDxe: convert to PciCapLibLaszlo Ersek2018-05-242-171/+103
| | | | | | | | | | | Replace the manual capability list parsing in OvmfPkg/PciHotPlugInitDxe with PciCapLib and PciCapPciSegmentLib API calls. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* OvmfPkg/PciHotPlugInitDxe: translate QEMU's resource reservation hintsLaszlo Ersek2017-10-032-6/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parse QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION from the bridges' conventional config spaces. Translate the fields as follows: * BusNumbers: * 0 -- no reservation; * (-1) -- firmware default, i.e. no reservation; * otherwise -- reserve the requested value. (NB, bus number reservation is not supposed to work before <https://bugzilla.tianocore.org/show_bug.cgi?id=656> is fixed.) * Io: * 0 -- no reservation; * (-1) -- keep our current default (512B); * otherwise -- round up the requested value and reserve that. * NonPrefetchable32BitMmio: * 0 -- no reservation; * (-1) -- keep our current default (2MB); * otherwise -- round up the requested value and reserve that. * Prefetchable32BitMmio: * 0 -- no reservation, proceed to Prefetchable64BitMmio; * (-1) -- firmware default, i.e. no reservation, proceed to Prefetchable64BitMmio; * otherwise -- round up the requested value and reserve that. (NB, if Prefetchable32BitMmio is reserved in addition to NonPrefetchable32BitMmio, then PciBusDxe currently runs into an assertion failure. Refer to <https://bugzilla.tianocore.org/show_bug.cgi?id=720>.) * Prefetchable64BitMmio: * only reached if Prefetchable32BitMmio was not reserved; * 0 -- no reservation; * (-1) -- firmware default, i.e. no reservation; * otherwise -- round up the requested value and reserve that. If QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION is missing, plus any time the rounding fails, fall back to the current defaults. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PciHotPlugInitDxe: add helper functions for setting up paddingsLaszlo Ersek2017-10-032-10/+156
| | | | | | | | | | | | | | | | | | | | | | Extract the SetIoPadding() and SetMmioPadding() functions, so that we can set EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR fields using parameter names and values that are more friendly than the original field names and their expected values. Introduce the HighBitSetRoundUp32() and HighBitSetRoundUp64() functions for calculating the last parameter ("SizeExponent") of SetIoPadding() and SetMmioPadding(). Put the new functions to use when requesting the default reservations. (In order to be consistent with a later patch, "SizeExponent" is calculated for SetIoPadding() with HighBitSetRoundUp64().) Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PciHotPlugInitDxe: generalize RESOURCE_PADDING compositionLaszlo Ersek2017-10-032-64/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PciHotPlugInitDxe has a static variable called "mPadding" (of type RESOURCE_PADDING), which describes two constant resource reservations: - MmioPadding: 2MB of non-prefetchable (hence 32-bit) MMIO space, - IoPadding: 512B of IO space. In the GetResourcePadding() member function of EFI_PCI_HOT_PLUG_INIT_PROTOCOL, the driver outputs a dynamically allocated verbatim copy of "mPadding", for PciBusDxe to consume in its ApplyResourcePadding() function. In a later patch, we're going to compose the set of resource reservations dynamically, based on QEMU hints. Generalize the RESOURCE_PADDING structure so that we may generate (or not generate) each resource type individually: - Replace the named "MmioPadding" and "IoPadding" fields in RESOURCE_PADDING with an array of descriptors, - remove "mPadding", - in GetResourcePadding(), request the same (default) reservations as before, as if we attempted and failed to fetch the QEMU hints. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PciHotPlugInitDxe: clean up addr. range for non-prefetchable MMIOLaszlo Ersek2017-10-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The non-prefetchable MMIO aperture of a bridge can never fall outside of the 32-bit address space. Namely, the MemoryBase and MemoryLimit fields in PCI_BRIDGE_CONTROL_REGISTER have type UINT16, and based on the PCI-to-PCI Bridge Architecture Spec, Chapter 3.2, the actual MMIO aperture is determined as in: NonPrefetchMemoryBase = (((MemoryBase & 0xFFF0u) >> 4) << 20) | 0x00000 NonPrefetchMemoryLimit = (((MemoryLimit & 0xFFF0u) >> 4) << 20) | 0xFFFFF In "OvmfPkg/PciHotPlugInitDxe", the "mPadding.MmioPadding.AddrSpaceGranularity" field is currently initialized to 64. According to the above, this is useless generality: a non-prefetchable MMIO reservation may only be satisfied from 32-bit address space. Update the field to 32. In practice this change makes no difference, because PciBusDxe already enforces the 32-bit limitation when it sees "non-prefetchable" from (SpecificFlag==0). Quoting commit 8aba40b79267 ("OvmfPkg: add PciHotPlugInitDxe", 2016-06-30): "regardless of our request for 64-bit MMIO reservation, it is downgraded to 32-bit". (See the Platform Init Spec 1.6, Volume 5, - Table 8. "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage", and - Table 11. "Memory Resource Flag (Resource Type = 0) Usage", for an explanation of the "mPadding.MmioPadding" fields.) Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Fixes: 8aba40b79267df761bd24d6874ae87f47a7bd3de Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg/PciHotPlugInitDxe: clean up protocol usage commentLaszlo Ersek2017-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | The driver always produces an instance of the EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The "SOMETIMES_PRODUCES" remark is an oversight from the original v1->v2 patch update; v2 should have stated "ALWAYS_PRODUCES": http://mid.mail-archive.com/1468242274-12686-5-git-send-email-lersek@redhat.com > Notes: > v2: > - drop the PcdPciBusHotplugDeviceSupport check, and the PcdLib > dependency with it [Jordan] Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Fixes: 8aba40b79267df761bd24d6874ae87f47a7bd3de Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* OvmfPkg: add PciHotPlugInitDxeLaszlo Ersek2016-07-132-0/+384
After IncompatiblePciDeviceSupportDxe, this is another small driver / protocol implementation that tweaks the behavior of the PCI bus driver in edk2. The protocol is specified in the Platform Init Spec v1.4a, Volume 5, Chapter 12.6 "PCI Hot Plug PCI Initialization Protocol". This implementation steers the PCI bus driver to reserve the following resources ("padding") for each PCI bus, in addition to the BARs of the devices on that PCI bus: - 2MB of 64-bit non-prefetchable MMIO aperture, - 512B of IO port space. The goal is to reserve room for devices hot-plugged at runtime even if the bridge receiving the device is empty at boot time. The 2MB MMIO size is inspired by SeaBIOS. The 512B IO port size is actually only 1/8th of the PCI spec mandated reservation, but the specified size of 4096 has proved wasteful (given the limited size of our IO port space -- see commit bba734ab4c7c). Especially on Q35, where every PCIe root port and downstream port qualifies as a separate bridge (capable of accepting a single device). Test results for this patch: - regardless of our request for 64-bit MMIO reservation, it is downgraded to 32-bit, - although we request 512B alignment for the IO port space reservation, the next upstream bridge rounds it up to 4096B. Cc: "Johnson, Brian J." <bjohnson@sgi.com> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Suggested-by: Andrew Fish <afish@apple.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 14:19:34 +0000