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* OvmfPkg/RiscVVirt: Add support for separate code and variable storeSunil V L2023-06-231-8/+6
| | | | | | | | | | | | | | | | | | | Currently, RiscVVirtQemu supports unified code and variable store mainly because only one pflash devices was available in qemu for EDK2. However, this doesn't allow to map the code part as read-only. With recent qemu enhancements, it is now possible for EDK2 to make use of both pflash devices in RISC-V virt machine. So, add support to create code and vars images separately. This also allows easy firmware code updates without losing the variable store. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andrei Warkentin <andrei.warkentin@intel.com> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* OvmfPkg/RiscVVirt: Add build files for Qemu Virt platformSunil V L2023-02-161-0/+41
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW - Leveraged from ArmVirtQemu Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Abner Chang <abner.chang@amd.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>