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* UefiCpuPkg: Move MigrateGdt from DiscoverMemory to TempRamDone. (CVE-2019-11098)Guomin Jiang2021-02-043-46/+0
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1614 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3160 The GDT still in flash with commit 60b12e69fb1c8c7180fdda92f008248b9ec83db1 after TempRamDone So move the action to TempRamDone event to avoid reading GDT from flash. Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuMp: Fix hang when StackGuard is enabled in 16-core cpuRay Ni2021-01-223-9/+7
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3167 When StackGuard is enabled, the CpuMp driver allocates known good stacks for all CPUs for DF# and PF# exceptions. It uses AllocatePool to do so. The size needed equals to 64KB = StackSize (2K) * ExceptionNumber (2) * NumberOfProcessors (16) However, AllocatePool max allocation size is less than 64K. To fix the issue, AllocatePages() is used. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg: Correct some typos.Guomin Jiang2020-07-282-3/+3
| | | | | | | | | | | | Correct some typos. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/CpuMpPei: Enable paging and set NP flag to avoid TOCTOU ↵Guomin Jiang2020-07-282-5/+30
| | | | | | | | | | | | | | | | | | (CVE-2019-11098) REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 To avoid the TOCTOU, enable paging and set Not Present flag so when access any code in the flash range, it will trigger #PF exception. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Guomin Jiang <guomin.jiang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/CpuMpPei: Add GDT migration support (CVE-2019-11098)Michael Kubacki2020-07-284-2/+60
| | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1614 Moves the GDT to permanent memory in a memory discovered callback. This is done to ensure the GDT authenticated in pre-memory is not fetched from outside a verified location after the permanent memory transition. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray2019-08-091-3/+3
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuMpPei: Produce EDKII_PEI_MP_SERVICES2_PPI.Eric Dong2019-07-294-7/+436
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Produce new EDKII_PEI_MP_SERVICES2_PPI service. It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuMpPei: Add missing CpuLib classMichael D Kinney2019-04-301-1/+2
| | | | | | | | | | | | The CpuMpPei module uses a services from the CpuLib class, but the CpuLib class is missing from the INF file. This update is required to use the new MpInitLibUp instance that does not use the CpuLib class. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-097-49/+7
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuMpPei: fix vs2012 build errorJian J Wang2018-09-261-0/+3
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1166 Visual Studio 2012 will complain uninitialized variable, StackBase, in the CpuPaging.c. This patch adds code to init it to zero and ASSERT check against 0. This is enough since uninit case will only happen during retrieving stack memory via gEfiHobMemoryAllocStackGuid. But this HOB will always be created in advance. Cc: Dandan Bi <dandan.bi@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuMpPei: support stack guard featureJian J Wang2018-09-104-17/+937
| | | | | | | | | | | | | | | | | | | | | | This feature is the same as Stack Guard enabled in driver CpuDxe but applies to PEI phase. Due to the specialty in PEI module dispatching, this driver is changed to do the actual initialization in notify callback of event gEfiPeiMemoryDiscoveredPpiGuid. This can let the stack guard apply to as most PEI drivers as possible. To let Stack Guard work, some simple page table management code are introduced to setup Guard page at base of stack for each processor. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuMpPei: Correct BIST PPI logic.Marvin H?user2018-07-241-10/+12
| | | | | | | | | | | | | Currently, the SecPlatformInformation2 PPI is installed when either there is none present or the present one doesn't lack data. Update the logic to only install the SecPlatformInformation2 PPI when it's not already installed so that an up-to-date PPI remains the only one and unchanged. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-282-5/+5
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg CpuMpPei: Update return status to follow spec.Eric Dong2017-07-072-2/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST DataJeff Fan2016-09-143-23/+46
| | | | | | | | | | | | | Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe driver to get CPU BIST data. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuMpPei: Fix BistData ouput errorJeff Fan2016-09-141-1/+1
| | | | | | | | | | | | | | ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x only output the low 4 bytes and keep the high 4 bytes in stack that will be output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to UINT32 could make BistData output correctly. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuMpPei: Add parameter BistInformationSizeJeff Fan2016-09-141-3/+10
| | | | | | | | | | | Add one OPTIONAL parameter BistInformationSize for GetBistInfoFromPpi(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
* UefiCpuPkg/CpuMpPei: Delete PeiMpServices.c and PeiMpServices.hJeff Fan2016-08-175-766/+727
| | | | | | | | | | | | | | | | | | Move the code in PeiMpServices.c & PeiMpServices.h to CpuMpPei.c & CpuMpPei.h. v3: 1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP 2. Add PeiMpInitLib.inf in DSC file Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuMpPei: Remove unused files and codesJeff Fan2016-08-1713-2669/+0
| | | | | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuMpPei: Consume MpInitLib to produce CPU MP PPI servicesJeff Fan2016-08-175-491/+112
| | | | | | | | | | | | | | | | | | | | | | | | Consume MP initialize library to produce CPU MP PPI, it could simply the code. Add STATIC for some internal functions to avoid build issue with the same functions name in PeiMpInit instance. They will be removed by the next patch. v4: 1. Update BistData type from UINT32 to EFI_HEALTH_FLAGS. v3: 1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP 2. Add PeiMpInitLib.inf in DSC file Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitionsJeff Fan2016-08-172-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | #define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h. Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from ArchitecturalMsr.h. v5: 1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuMpPei: Remove PmodeOffset and LmodeOffsetJeff Fan2016-07-148-25/+17
| | | | | | | | | | | | Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Remove un-used variables and functionsJeff Fan2016-07-148-156/+0
| | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Do not load new GDT tableJeff Fan2016-07-141-5/+1
| | | | | | | | | | | | Do not load the new GDT table and just to use the exiting BSP's GDT table set up by SEC phase. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/X64: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-93/+71
| | | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't the CS/DS of protected mode. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST valueJeff Fan2016-07-141-4/+3
| | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei/Ia32: Use CodeSegment and DataSegment fieldsJeff Fan2016-07-142-34/+48
| | | | | | | | | | | | Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode MACROs. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Add CodeSegment and DataSegment fieldsJeff Fan2016-07-144-4/+12
| | | | | | | | | | | | Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set to the values of current BSP's CS and DS. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Giri Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Remove unnecessary variableJeff Fan2016-07-132-4/+0
| | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Dump message if microcode signature not matchedJeff Fan2016-07-134-25/+31
| | | | | | | | | | | | | Verification microcode signature is one enhancement and not one requirement from IA32 SDM. This update is just to dump debug message instead of ASSERT() if the updated microcode signature does not match the loaded microcode signature. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg/CpuMpPei: Skip microcode check/load if it has been loadedJeff Fan2016-07-131-0/+9
| | | | | | | | | | | | | | Actually, there is only one microcode region in platform. If microcode has been loaded, its signature will not be zero and should be loaded successfully. We needn't to check microcode region and load microcode again. This update is to skip checking/loading microcode if current microcode signature is not zero. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
* UefiCpuPkg CpuMpPei: Update INF to refer to NASM source fileLiming Gao2016-07-111-6/+4
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Fix typos in commentsGiri P Mudusuru2016-07-111-1/+1
| | | | | | | | | - becasue to because Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuMpPei: Consume CpuExceptionHandlerLibJeff Fan2016-06-013-4/+26
| | | | | | | | | Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuMpPei: Fix potential AP mwait wakeup issueJeff Fan2016-04-111-7/+35
| | | | | | | | | | | | | | | | | | | | | | If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait instruction. BSP will wakeup AP by write start-up signal in monitor address. However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP will check if BSP wants to wakeup itself really. If not, AP will continue to execute mwait to C-State. One potential issue: BSP may not recognize AP was wakeup from C-State by other event and BSP still writes start-up signal to wakeup AP. But AP does not aware it and still execute mwait instruction to C-State. So, AP cannot be wakeup on this case. This fix is let AP to clear start-up signal when it really is wakeup to execute AP function. And BSP will write start-up signal till AP clears it. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: CpuMpPei: remove set but unused variablesLaszlo Ersek2016-03-251-2/+1
| | | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuMpPei: Load microcode if found newer revisionJeff Fan2016-03-031-8/+10
| | | | | | | | | | | | | Current implementation only loads the latest revision if there is no microcode loaded. Per IA32 User Manual, we should load the newer revision by comparing the existing microcode loaded with the updating revision. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuMpPei: Remove un-used AsmCliHltLoop()Jeff Fan2015-12-185-34/+0
| | | | | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19347 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Wake up APs by proper methodJeff Fan2015-12-184-12/+42
| | | | | | | | | | | | | | | | | If ApLoopMode is ApInHltLoop, BSP will send INIT-SIPI-SIPI to wake up APs. If ApLoopMode is ApInMwaitLoop or ApInRunLoop, BSP will write one semaphore to wake up APs. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19346 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Place APs in proper loop mode after AP executionJeff Fan2015-12-183-46/+106
| | | | | | | | | | | | | | | | | | After AP function is executed, we will place AP in proper loop mode. Because AP maybe waken up by SMI or other reasons. We need to read signature in monitor buffer to check if APs is waken up by BSP. If it is not waken up by BSP, we will continue to place them into proper loop mode. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19345 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Prepare for monitor bufferJeff Fan2015-12-182-2/+26
| | | | | | | | | | | | | | | | Get AP loop mode to prepare for the monitor buffer required for ApInMwaitLoop and ApInRunLoop. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19344 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Add GetApLoopMode() to get AP loop modeJeff Fan2015-12-183-0/+55
| | | | | | | | | | | | | | | | | | | | Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop. GetApLoopMode() also return the largest line size required. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19343 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Fix pack(1) issue on x64 archJeff Fan2015-12-181-1/+3
| | | | | | | | | | | | | | | | | | Packing alignment for MP_CPU_EXCHANGE_INFO should be 1. This should be typo when check-in CpuMpPei driver. IA32 arch MP_CPU_EXCHANGE_INFO is luckly pack(1). It leads CpuMpPei x64 version hung. Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19340 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen2015-12-152-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Add missing point at function headerJeff Fan2015-12-081-2/+2
| | | | | | | | | Cc: Qiu Shumin <shumin.qiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19165 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Fix typo and add some commentsJeff Fan2015-12-021-2/+5
| | | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19090 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Save/Restore CRx/DRx register for APs waking upJeff Fan2015-12-021-0/+10
| | | | | | | | | | | | | | | PeiStartupAllAPs()/PeiStartupThisAP() will send INIT-SIPI-SIPI to wakeup APs to execute AP function. However, some registers will be reset after APs received INIT IPI. We need to restore some registers (For example, CRx/DRx) manually after APs wakeup. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19089 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Sync BSP's CRx to APs when initializationJeff Fan2015-12-021-0/+5
| | | | | | | | | | | | Save BSP's volatile register and sync CRx register to APs when AP 1st wake up. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19088 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Set AP state to CpuStateIdle after initializationJeff Fan2015-12-021-4/+6
| | | | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19087 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/CpuMpPei: Add CPU_VOLATILE_REGISTERS & worker functionsJeff Fan2015-12-022-0/+80
| | | | | | | | | | | | | | | | | Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored after APs received INIT IPI. Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to save/restore CRx and DRx. It also check if Debugging Extensions supported or not. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19086 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-27 13:57:10 +0000