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* UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.Eric Dong2018-10-221-4/+17
| | | | | | | | | | | | | | | | | | V4 changes: 1. Update comments. v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition to AcpiCpuData.h. 2. Add comments for CPU_FEATURE_BEFORE/CPU_FEATURE_AFTER. v1 changes: Add new core/package dependence types which consumed by different MSRs. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.Eric Dong2018-10-221-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition here from RegisterCpuFeaturesLib.h file. 2. Add Invalid type for REGISTER_TYPE which will be used in code. v2 changes: 1. Add more description about why we do this change. 2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it will be share between PEI and DXE. v1 Changes: In order to support semaphore related logic, add new definition for it. In a system which has multiple cores, current set register value task costs huge times. After investigation, current set MSR task costs most of the times. Current logic uses SpinLock to let set MSR task as an single thread task for all cores. Because MSR has scope attribute which may cause GP fault if multiple APs set MSR at the same time, current logic use an easiest solution (use SpinLock) to avoid this issue, but it will cost huge times. In order to fix this performance issue, new solution will set MSRs base on their scope attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A must been set after MSR B has been set. Also MSR B is package scope level and MSR A is thread scope level. If system has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 and thread 2 like below: Thread 1 Thread 2 MSR B N Y MSR A Y Y If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but at this time, MSR B not been executed yet by thread 2. system may trig exception at this time. In order to fix the above issue, driver introduces semaphore logic to control the MSR execute sequence. For the above case, a semaphore will be add between MSR A and B for all threads. Semaphore has scope info for it. The possible scope value is core or package. For each thread, when it meets a semaphore during it set registers, it will 1) release semaphore (+1) for each threads in this core or package(based on the scope info for this semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based on the scope info for this semaphore). With these two steps, driver can control MSR sequence. Sample code logic like below: // // First increase semaphore count by 1 for processors in this package. // for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); } // // Second, check whether the count has reach the check number. // for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { LibWaitForSemaphore (&SemaphorePtr[ApOffset]); } Platform Requirement: 1. This change requires register MSR setting base on MSR scope info. If still register MSR for all threads, exception may raised. Known limitation: 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature PEI instance not works after this change. We plan to support async mode for PEI in phase 2 for this task. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Change to DOS format file.Eric Dong2018-09-301-272/+272
| | | | | | | | | | | | | Follow EDKII coding style, change file format to dos style. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1213 Cc: Dandan Bi <dandan.bi@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.Eric Dong2018-09-261-9/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep the ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes: Changes includes: 1. Update MSR structure definition, change some reserved fields to useful fields: 1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER 2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER 2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range. Old definition like below: typedef union { /// /// Individual bit fields /// struct { /// /// [Bits 15:0] LVL_2 Base Address (R/W). /// UINT32 Lvl2Base:16; /// /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the /// maximum C-State code name to be included when IO read to MWAIT /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 /// is the max C-State to include 110b - C6 is the max C-State to include. /// UINT32 CStateRange:3; UINT32 Reserved1:13; UINT32 Reserved2:32; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; /// /// All bit fields as a 64-bit value /// UINT64 Uint64; } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; This patch make below changes for this data structure, it expand "CStateRange" field width. old one: UINT32 CStateRange:3; UINT32 Reserved1:13; new one: UINT32 CStateRange:7; UINT32 Reserved1:9; Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.Eric Dong2018-09-261-2/+12
| | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes includes: 1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old ↵Eric Dong2018-09-261-10/+24
| | | | | | | | | | | | | | | | | | | | one. Changes includes: 1. Change MSR name: 1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0 2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1 2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility. 1. Define old MSR like below style: #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.Eric Dong2018-09-261-13/+27
| | | | | | | | | | | | | | | | | | Changes includes: 1. Change MSR name: 1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0 2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1 2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility 1. Use below coding style to define old MSR #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE_ROB_CR_BKUPTMPDR6 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | Changes includes: 1. Remove MSR which not existed in 2018-05 version spec: MSR_P6_ROB_CR_BKUPTMPDR6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.Eric Dong2018-09-261-60/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE2_BBL_CR_CTL3 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.Eric Dong2018-09-261-0/+64
| | | | | | | | | | | | | Changes includes: 1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.Eric Dong2018-09-261-1/+1546
| | | | | | | | | | | | | | Changes includes: 1. Add new MSR definitions. 2. Add support platform info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.Eric Dong2018-09-261-3/+246
| | | | | | | | | | | | | | | | | | Changes includes: 1. Add new MSR definition: 1. MSR_XEON_PHI_PPIN_CTL 2. MSR_XEON_PHI_PPIN 3. MSR_XEON_PHI_MISC_FEATURE_ENABLES 4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 2. Add DisplayModule == 0x85 supports. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.Eric Dong2018-09-263-2/+164
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.Eric Dong2018-09-261-0/+48
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for ↵Eric Dong2018-09-262-3/+276
| | | | | | | | | | | | | | | goldmont plus microarchitecture. Changes includes: 1. Add new MSR file which used for goldmont plus microarchitecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr: Update reference spec info.Eric Dong2018-09-2621-372/+359
| | | | | | | | | | | | | | | | | | Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4 chapter 2. Current MSR's comments need to be updated to reference the new chapter info. Changes includes: 1. Update referenced chapter info from some MSRs. 2. Update referenced SDM version info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/AcpiCpuData.h: Remove AcpiNVS and Below 4G limitation.Eric Dong2018-08-161-22/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI_CPU_DATA structure first introduced to save data in normal boot phase. Also this data will be used in S3 phase by one PEI driver. So in first phase, this data is been defined to use ACPI NVS memory type and must below 4G. Later in order to fix potential security issue, PiSmmCpuDxeSmm driver added logic to copy ACPI_CPU_DATA (except ResetVector and Stack buffer) to smram at smm ready to lock point. ResetVector must below 1M and Stack buffer is write only in S3 phase, so these two fields not copy to smram. Also PiSmmCpuDxeSmm driver owned the task to restore the CPU setting and it's a SMM driver. After above change, the acpi nvs memory type and below 4G limitation is no longer needed. This change remove the limitation in the comments for ACPI_CPU_DATA definition. Cc: Marvin Häuser <Marvin.Haeuser@outlook.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-281-23/+23
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/MtrrLib: Add comments to recommend to use batch-set APIRuiyu Ni2018-01-241-0/+10
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() is a batch-set API. When setting multiple ranges of memory attributes, the single-set API (MtrrSetMemoryAttributeInMtrrSettings and MtrrSetMemoryAttribute) may fail, but batch-set API may succeed. Add comments to recommend caller to use batch-set API when setting multiple ranges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MtrrLib: Update the comments for RETURN_BUFFER_TOO_SMALLRuiyu Ni2018-01-241-3/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-271-5/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-131-0/+5
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-302-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Make comments align with functionDandan Bi2017-10-241-1/+1
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settingsRuiyu Ni2017-10-161-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new algorithm converts the problem calculating optimal MTRR settings (using least MTRR registers) to the problem finding the shortest path in a graph. The memory required in extreme but rare case can be up to 256KB, so using local stack buffer is impossible considering current DxeIpl only allocates 128KB stack. The patch changes existing MtrrSetMemoryAttributeInMtrrSettings() and MtrrSetMemoryAttribute() to use the 4-page stack buffer for calculation. The two APIs return BUFFER_TOO_SMALL when the buffer is too small for calculation. The patch adds a new API MtrrSetMemoryAttribute*s*InMtrrSettings() to set multiple-range attributes in one function call. Since every call to MtrrSetMemoryAttributeInMtrrSettings (without-s) or MtrrSetMemoryAttribute() requires to calculate the MTRRs for the whole physical memory, combining multiple calls in one API can significantly reduce the calculation time. In theory, if N times of call to without-s API costs N seconds, the new API only costs 1 second. The new API uses the buffer supplied from caller to calculate MTRRs and returns BUFFER_TOO_SMALL when the buffer is too small for calculation. Test performed: 1. Random test a. Generate random memory settings, use the new algorithm to calculate the MTRRs. b. Read back the MTRRs and check the memory settings match the desired memory settings. c. Repeat the above #1 and #2 100000 times. 2. OVMF 32PEI + 64DXE boot to shell. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.Eric Dong2017-08-281-1/+78
| | | | | | | | | | | | Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg MtrrLib: Remove deprecated micro.Eric Dong2017-08-071-27/+0
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Add Processor Trace feature definition.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Msr: Add a missing IvyBridge processor signatureHao Wu2017-08-041-1/+2
| | | | | | | | | | | This commit modifies the CPUID signature check MACRO for IvyBridge processor by adding a missing DisplayModel 0x3E. The missing one appears at Section 35.10.1 to Section 35.10.3 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Add definition for LMCE feature.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Remove deprecated CPU feature.Eric Dong2017-07-201-1/+0
| | | | | | | | | | | | Senter feature could not be a single feature, it has been merge to Smx feature, so remove it. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Add feature definition for PPIN.Eric Dong2017-07-201-0/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Fix coding style issuesDandan Bi2017-06-291-2/+2
| | | | | | | | | Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add CPUID definitions for AMD.Leo Duran2017-06-261-9/+590
| | | | | | | | | | Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSRBrijesh Singh2017-06-263-0/+253
| | | | | | | | | | | | | | | The patch defines AMD's Memory Encryption Information CPUID leaf and SEV status MSR. The complete description for CPUID leaf is available in APM volume 2, Section 15.34. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leo Duran <leo.duran@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuFeatures: Change CPU features name to follow IA32 SDMJeff Fan2017-04-071-2/+2
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/CpuFeatures: Change files format to DOSJeff Fan2017-04-053-570/+570
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/MtrrLib: Add CacheInvalid enum type to MtrrLib.hRuiyu Ni2017-03-311-1/+2
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/MtrrLib: Correct typo in comments and remove TABsRuiyu Ni2017-03-311-7/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Fix the function header issuesJeff Fan2017-03-281-29/+31
| | | | | | | | Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO addressJeff Fan2017-03-271-5/+7
| | | | | | | | | | | | | | | | | | | The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB. This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field HighIndex to indicate the high 32bit MMIO address and original Index still indicate the low 32bit MMIO address. This update makes use of original padding space between ValidBitLength and Value to add HighIndex. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64Jeff Fan2017-03-271-2/+2
| | | | | | | | | | | | | | The input parameter Index of PreSmmCpuRegisterTableWrite() and CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB. This fix is to define Index to UINT64 instead of UINT32. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/Include/Library: Add Register CPU Features LibraryJeff Fan2017-03-221-0/+516
| | | | | | | | | | | | | | | | | Register CPU Features Library is used to register/manage/program CPU features. NULL CPU features library instance could consume it register CPU features functions. CPU Feature module could consume this library to detect/analysis/program CPU features on BSP/APs. v4: Fix GCC build issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuidJeff Fan2017-03-221-0/+26
| | | | | | | | | | | | | | | | GUID gEdkiiCpuFeaturesInitDoneGuid is used to indicate if CPU features have been initialized. On PEI phase, one gEdkiiCpuFeaturesInitDoneGuid PPI will be installed after CPU features initialized. On DXE phase, one gEdkiiCpuFeaturesInitDoneGuid Protocol will be installed after CPU features initialized. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuidJeff Fan2017-03-221-0/+26
| | | | | | | | | | | | | | | | GUID gEdkiiCpuFeaturesSetDoneGuid is used to indicate if CPU feature related setting are set finished. For example, PCD PcdCpuFeaturesUserConfiguration. On PEI phase, one gEdkiiCpuFeaturesSetDoneGuid PPI will be installed after platform set CPU feature setting. On DXE phase, one gEdkiiCpuFeaturesSetDoneGuid Protocol will be installed after platform set CPU feature setting. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/Msr: Add CPUID signature check MACROsJeff Fan2017-03-2220-20/+365
| | | | | | | | | | | | All model-specific MSRs are related to processor signatures that are defined in each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry typeJeff Fan2017-03-221-3/+3
| | | | | | | | | | | | | | | Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry. This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and make RegisterTableEntry is fixed length. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii charactersHao Wu2016-12-201-1/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Add STM GUIDs, Protocols, and PCDsMichael Kinney2016-12-195-0/+1431
| | | | | | | | | | | | | | | | * Add GUIDed HOB that described MSEG region in SMRAM * Add SM Monitor Init Protocol * Add PCD to configure size of SMM exception stack * Add PCD to configure MSEG region size if it is not described by the gMsegSmramGuid GUIDed HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 21:41:25 +0000