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* UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid"Ruiyu Ni2018-09-261-16/+13
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1187 The patch reverts 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8 "UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid". Microsoft Windows will report an error in event manager if MTRR usage is different across hibernate even when the difference is in an non valid MTRR pair. This seems like a bug in Windows but for compatibility and servicing reasons we think a change in UEFI would wise. A Windows change has already been submitted for the next iteration (2019 time frame). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com>
* UefiCpuPkg/PeiCpuException: Fix coding style issueRuiyu Ni2018-09-101-3/+3
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/MpInitLib: fix register restore issue in AP wakeupJian J Wang2018-09-101-2/+6
| | | | | | | | | | | | | | | | | | | | The conflict issues are introduced by Stack Guard feature enabled for PEI. The first is CR0 which should be restored after CR3 and CR4. Another is TR which should not be passed from BSP to AP during init phase. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: support stack switch for PEI exceptionsJian J Wang2018-09-102-1/+30
| | | | | | | | | | | | | | | | | | | Stack Guard needs to setup stack switch capability to allow exception handler to be called with good stack if stack overflow is detected. This patch update InitializeCpuExceptionHandlersEx() to allow pass extra initialization data used to setup exception stack switch for specified exceptions. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: "Ware, Ryan R" <ryan.r.ware@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix ECC issues.Eric Dong2018-09-064-4/+4
| | | | | | | | | Fix trailing white spaces and invalid line ending issue. Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Avoid calling PEI services from APRuiyu Ni2018-09-032-29/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When an exception happens in AP, system hangs at GetPeiServicesTablePointer(), complaining the PeiServices retrieved from memory before IDT is NULL. Due to the following commit: c563077a380437c114aba4c95be65eb963ebc1f3 * UefiCpuPkg/MpInitLib: Avoid calling PEI services from AP the IDT used by AP no longer preserve PeiServices pointer in the very beginning. But the implementation of PeiExceptionHandlerLib still assumes the PeiServices pointer is there, so the assertion happens. The patch fixes the exception handler library to not call PEI services from AP. The patch duplicates the #0 exception stub header in an allocated pool but with extra 4-byte/8-byte to store the exception handler data which was originally stored in HOB. When AP exception happens, the code gets the exception handler data from the exception handler for #0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Fan Jeff <vanjeff_919@hotmail.com>
* CpuExceptionHandlerLib: Add comments to make code more readableRuiyu Ni2018-09-033-10/+18
| | | | | | | | | | Today's implementation of handling HOOK_BEFORE and HOOK_AFTER is a bit complex. More comments is better. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handlerJian J Wang2018-08-303-3/+12
| | | | | | | | | | | | | | | | | | | Once the #PF handler has set the page to be 'present', there should be a way to reset it to 'not-present'. 'TF' bit in EFLAGS can be used for this purpose. 'TF' bit will be set in interrupted function context so that it can be triggered once the cpu control returns back to the instruction causing #PF and re-execute it. This is an necessary step to implement non-stop mode for Heap Guard and NULL Pointer Detection feature. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/SmmCpuFeaturesLib: [CVE-2017-5715] Stuff RSB before RSMHao Wu2018-08-216-5/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093 Return Stack Buffer (RSB) is used to predict the target of RET instructions. When the RSB underflows, some processors may fall back to using branch predictors. This might impact software using the retpoline mitigation strategy on those processors. This commit will add RSB stuffing logic before returning from SMM (the RSM instruction) to avoid interfering with non-SMM usage of the retpoline technique. After the stuffing, RSB entries will contain a trap like: @SpecTrap: pause lfence jmp @SpecTrap A more detailed explanation of the purpose of commit is under the 'Branch target injection mitigation' section of the below link: https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation Please note that this commit requires further actions (BZ 1091) to remove the duplicated 'StuffRsb.inc' files and merge them into one under a UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Combine implementation.Eric Dong2018-08-164-218/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V1 changes: > Current code logic can't confirm CpuS3DataDxe driver start before > CpuFeaturesDxe driver. So the assumption in CpuFeaturesDxe not valid. > Add implementation for AllocateAcpiCpuData function to remove this > assumption. V2 changes: > Because CpuS3Data memory will be copy to smram at SmmReadToLock point, > so the memory type no need to be ACPI NVS type, also the address not > limit to below 4G. > This change remove the limit of ACPI NVS memory type and below 4G. V3 changes: > Remove function definition in header file. > Add STATIC in function implementation. Pass OS boot and resume from S3 test. Bugz: https://bugzilla.tianocore.org/show_bug.cgi?id=959 Reported-by: Marvin Häuser <Marvin.Haeuser@outlook.com> Suggested-by: Fan Jeff <vanjeff_919@hotmail.com> Cc: Marvin Häuser <Marvin.Haeuser@outlook.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Removing ipf which is no longer supported from edk2.Chen A Chen2018-08-141-3/+3
| | | | | | | | | | Merge [Sources.Ia32, Sources.X64] to [Sources] after removing IPF. Also change other similar parts in this file. Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Not use disabled AP when call StartAllAPs.Eric Dong2018-07-263-12/+26
| | | | | | | | | | | | | | | | | | Base on UEFI spec requirement, StartAllAPs function should not use the APs which has been disabled before. This patch just change current code to follow this rule. V3 changes: Only called by StartUpAllAps, WakeUpAp will not wake up the disabled APs, in other cases also need to include the disabled APs, such as CpuDxe driver start up and ChangeApLoopCallback function. WakeUpAP() is called with (Broadcast && WakeUpDisabledAps) from MpInitLibInitialize(), CollectProcessorCount() and MpInitChangeApLoopCallback() only. The first two run before the PPI or Protocol user has a chance to disable any APs. The last one runs in response to the ExitBootServices and LegacyBoot events, after which the MP protocol is unusable. For this reason, it doesn't matter that an originally disabled AP's state is not restored to Disabled, when WakeUpAP() is called with (Broadcast && WakeUpDisabledAps). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Remove StartCount and volatile definition.Eric Dong2018-07-262-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The patch includes below changes: (1) It removes "volatile" from RunningCount, because only the BSP modifies it. (2) When we detect a timeout in CheckAllAPs(), and collect the list of failed CPUs, the size of the list is derived from the following difference, before the patch: StartCount - FinishedCount where "StartCount" is set by the BSP at startup, and FinishedCount is incremented by the APs themselves. Here the patch replaces this difference with StartCount - RunningCount that is, the difference is no more calculated from the BSP's startup counter and the AP's shared finish counter, but from the RunningCount measurement that the BSP does itself, in CheckAllAPs(). (3) Finally, the patch changes the meaning of RunningCount. Before the patch, we have: - StartCount: the number of APs the BSP stars up, - RunningCount: the number of finished APs that the BSP collected After the patch, StartCount is removed, and RunningCount is *redefined* as the following difference: OLD_StartCount - OLD_RunningCount Giving the number of APs that the BSP started up but hasn't collected yet. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Remove redundant CpuStateFinished State.Eric Dong2018-07-262-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | Current CPU state definition include CpuStateIdle and CpuStateFinished. After investigation, current code can use CpuStateIdle to replace the CpuStateFinished. It will reduce the state number and easy for maintenance. > Before this patch, the state transitions for an AP are: > > Idle ----> Ready ----> Busy ----> Finished ----> Idle > [BSP] [AP] [AP] [BSP] > > After the patch, the state transitions for an AP are: > > Idle ----> Ready ----> Busy ----> Idle > [BSP] [AP] [AP] Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Fix VS2012 build failureEric Dong2018-07-201-0/+5
| | | | | | | Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Remove useless code.Eric Dong2018-07-201-15/+0
| | | | | | | | | | | Remove the useless code error added by change 58942277bcbf41abda5f6e3a1c89d571105d5983. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Optimize get processor number performance.Eric Dong2018-07-201-1/+4
| | | | | | | | | | | | | | | | Current function has low performance because it calls GetApicId in the loop, so it maybe called more than once. New logic call GetApicId once and base on this value to search the processor. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Fix S3 resume hang issue.Eric Dong2018-07-194-2/+116
| | | | | | | | | | | | | | | | | | | | | | | | When resume from S3 and CPU loop mode is MWait mode, if driver calls APs to do task at EndOfPei point, the APs can't been wake up and bios hang at that point. The root cause is PiSmmCpuDxeSmm driver wakes up APs with HLT mode during S3 resume phase to do SMM relocation. After this task, PiSmmCpuDxeSmm driver not restore APs context which make CpuMpPei driver saved wake up buffer not works. The solution for this issue is let CpuMpPei driver hook S3SmmInitDone ppi notification. In this notify function, it check whether Cpu Loop mode is not HLT mode. If yes, CpuMpPei driver will set a flag to force BSP use INIT-SIPI -SIPI command to wake up the APs. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Load uCode once for each core.Eric Dong2018-07-181-0/+9
| | | | | | | | | | | | | | | The SDM requires only one thread per core to load the microcode. This change enables this solution. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Use BSP uCode for APs if possible.Eric Dong2018-07-183-7/+45
| | | | | | | | | | | | | | | Search uCode costs much time, if AP has same processor type with BSP, AP can use BSP saved uCode info to get better performance. This change enables this solution. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Relocate uCode to memory to save time.Eric Dong2018-07-181-1/+32
| | | | | | | | | | | | | | | | | | | Read uCode from memory has better performance than from flash. But it needs extra effort to let BSP copy uCode from flash to memory. Also BSP already enable cache in SEC phase, so it use less time to relocate uCode from flash to memory. After verification, if system has more than one processor, it will reduce some time if load uCode from memory. This change enable this optimization. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Avoid calling PEI services from APNi, Ruiyu2018-07-122-14/+63
| | | | | | | | | | | | | | | | | | | | | | | | | Today's MpInitLib PEI implementation directly calls PeiServices->GetHobList() from AP which may cause racing issue. This patch fixes this issue by duplicating IDT for APs. Because CpuMpData structure is stored just after IDT, the CpuMPData address equals to IDTR.BASE + IDTR.LIMIT + 1. v2: 1. Add ALIGN_VALUE() on BufferSize. 2. Add ASSERT() to make sure no memory usage outside of the allocated buffer. 3. Add more comments in InitConfig path when restoring CpuData[0].VolatileRegisters. Cc: Jeff Fan <vanjeff_919@hotmail.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Fish Andrew <afish@apple.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Removing ipf which is no longer supported from edk2.chenc22018-06-292-225/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing rules for Ipf sources file: * Remove the source file which path with "ipf" and also listed in [Sources.IPF] section of INF file. * Remove the source file which listed in [Components.IPF] section of DSC file and not listed in any other [Components] section. * Remove the embedded Ipf code for MDE_CPU_IPF. Removing rules for Inf file: * Remove IPF from VALID_ARCHITECTURES comments. * Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section. * Remove the INF which only listed in [Components.IPF] section in DSC. * Remove statements from [BuildOptions] that provide IPF specific flags. * Remove any IPF sepcific sections. Removing rules for Dec file: * Remove [Includes.IPF] section from Dec. Removing rules for Dsc file: * Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC. * Remove any IPF specific sections. * Remove statements from [BuildOptions] that provide IPF specific flags. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-2827-152/+152
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/LocalApicLib: Exclude second SendIpi sequence on AMD processors.Eric Dong2018-06-192-8/+16
| | | | | | | | | | | | | | | | | On AMD processors the second SendIpi in the SendInitSipiSipi and SendInitSipiSipiAllExcludingSelf routines is not required, and may cause undesired side-effects during MP initialization. This patch leverages the StandardSignatureIsAuthenticAMD check to exclude the second SendIpi and its associated MicroSecondDelay (200). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leo Duran <leo.duran@amd.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove X86 ASM and S filesLiming Gao2018-06-0714-1936/+6
| | | | | | | | | | | | | | | NASM has replaced ASM and S files. 1. Remove ASM from all modules expect for the ones in ResetVector directory. The ones in ResetVector directory are included by Vtf0.nasmb. They are also nasm style. 2. Remove S files from the drivers only. 3. https://bugzilla.tianocore.org/show_bug.cgi?id=881 After NASM is updated, S files can be removed from Library. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeatures: Follow SDM for MAX CPUID feature detectRuiyu Ni2018-05-281-2/+2
| | | | | | | | | | | | | | | According to IA manual: "Before setting this bit (MSR_IA32_MISC_ENABLE[22]) , BIOS must execute the CPUID.0H and examine the maximum value returned in EAX[7:0]. If the maximum value is greater than 2, this bit is supported." We need to fix our current detection logic to compare against 2. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg MpInitLib: Fix typo "sCPUID" to "CPUID"Star Zeng2018-04-251-2/+2
| | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Disable interrupt at ExitBootServices AP MwaitHao Wu2018-03-202-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Within function ApWakeupFunction(): When source level debugger is enabled, AP interrupts will be enabled by EnableDebugAgent(). Then the AP function will be executed by: Procedure (Parameter); After the AP function returns, AP interrupts will be disabled when the APs are placed in loop mode (both HltLoop and MwaiLoop). However, at ExitBootServices, ApWakeupFunction() is called with 'Procedure' equals to RelocateApLoop(). (ExitBootServices callback registered within InitMpGlobalData()) RelocateApLoop() never returns, so it has to disable the AP interrupts by itself. However, we find that interrupts are only disabled for the HltLoop case, but not for the MwaitLoop case (within file MpFuncs.nasm). This commit adds the missing disabling of AP interrupts for MwaitLoop. Also, for X64, this commit will disable the interrupts before switching to 32-bit mode. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg CpuExceptionHandlerLib: use FixedPcdGetSize() as the macro valueLiming Gao2018-03-161-3/+3
| | | | | | | | | | | | FixedPcdGetSize() is used as the macro value, PcdGetSize() is used as global variable or function. Here usage is to access macro value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Wang Jian J <jian.j.wang@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/MpInitLib: put mReservedApLoopFunc in executable memoryJian J Wang2018-03-081-4/+34
| | | | | | | | | | | | | | | | | | if PcdDxeNxMemoryProtectionPolicy is enabled for EfiReservedMemoryType of memory, #PF will be triggered for each APs after ExitBootServices in SCRT test. The root cause is that AP wakeup code executed at that time is stored in memory of type EfiReservedMemoryType (referenced by global mReservedApLoopFunc), which is marked as non-executable. This patch fixes this issue by setting memory of mReservedApLoopFunc to be executable immediately after allocation. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Fix coding style issueDandan Bi2018-03-081-1/+1
| | | | | | | | | | | | | Boolean values do not need to use explicit comparisons to TRUE or FALSE. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: fix incorrect init of exception stackJian J Wang2018-02-281-1/+1
| | | | | | | | | | | | | | | | | | This issue is introduced at following commit, which tried to add stack switch support on behalf of Stack Guard feature. 0ff5aa9cae1ea276668fa4398d047aa9fda3c2c7 The field KnownGoodStackTop in CPU_EXCEPTION_INIT_DATA is initialized to the start address of array mNewStack. This is wrong. It must be the end of mNewStack. This patch fixes this mistake. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabledRuiyu Ni2018-02-091-15/+17
| | | | | | | | | | | Today's McaInitialize() doesn't check State value before initialize MCi_CTL and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttlingRuiyu Ni2018-02-081-29/+23
| | | | | | | | | | | | | | | Today's implementation only assumes SandyBridge CPU supports Extended On-Demand Clock Modulation Duty Cycle. Actually it is supported when CPUID.06h.EAX[5] == 1. When platform requests 50% throttling, it causes value 1000b set to the low-4 bits of IA32_CLOCK_MODULATION. But the wrong code sets 1000b to bits[1-3] which causes assertion. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <vanjeff_919@hotmail.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: force flushing TLB for AP in mwait loop modeJian J Wang2018-01-291-0/+7
| | | | | | | | | | | | | | | | | | | | The reason doing this is that we found that calling StartupAllAps() to flush TLB for all APs in CpuDxe driver after changing page attributes will spend a lot of time to complete. If there are many page attributes update requests, the whole system performance will be slowed down explicitly, including any shell command and UI operation. The solution is removing the flush operation for AP in CpuDxe driver. Since TLB is always flushed in HLT loop mode, we just need to enforce a TLB flush for mwait loop mode. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: fix AP init issue in 64-bit PEIJian J Wang2018-01-291-4/+5
| | | | | | | | | | | | | | | | | | | | This issue is introduced by a patch at f32bfe6d061420a15bac6083063d227c567e6388 The above patch miss the case of 64-bit PEI, which will link X64/MpFuncs.nasm instead of Ia32/MpFuncs.nasm. For X64/MpFuncs.nasm, ExchangeInfo->ModeHighMemory should be always initialized no matter if separate wakeup buffer is allocated or not. Ia32/MpFuncs.nasm will not need ModeHighMemory during AP init. So the changes made in this patch should not affect the functionality of it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MpInitLib: Make sure AP uses correct StartupApSignalStar Zeng2018-01-261-0/+9
| | | | | | | | | | | | | | | | Every processor's StartupApSignal is initialized in MpInitLibInitialize() before calling CollectProcessorCount(). When SortApicId() is called from CollectProcessorCount(), AP Index is re-assigned by APIC ID. But SortApicId() forgets to set the correct StartupApSignal when sorting the AP. The patch fixes this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com>
* UefiCpuPkg/CpuExceptionHandler: Init serial port before context dumpRuiyu Ni2018-01-262-2/+10
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/MpInitLib: fix issue in wakeup buffer initializationJian J Wang2018-01-252-10/+11
| | | | | | | | | | | | | | | | | | | | To fix an issue in which enabling NX feature will mark the AP wakeup buffer as non-executable and fail the AP init, the buffer was split into two part: the lower part in memory within 1MB and the higher part within allocated executable memory (EfiBootServicesCode). But the address of higher part memory was stored in lower part memory, which is actually shared with legacy components and will be overwritten by LegacyBiosDxe driver if CSM is enabled. This patch fixes this issue by storing the address of higher part memory in CpuMpData instead of ExchangeInfo. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Add comments to recommend to use batch-set APIRuiyu Ni2018-01-241-0/+10
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() is a batch-set API. When setting multiple ranges of memory attributes, the single-set API (MtrrSetMemoryAttributeInMtrrSettings and MtrrSetMemoryAttribute) may fail, but batch-set API may succeed. Add comments to recommend caller to use batch-set API when setting multiple ranges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MtrrLib: Update the comments for RETURN_BUFFER_TOO_SMALLRuiyu Ni2018-01-241-2/+6
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/PeiMpLib: Fix a system hang-in-pei issue.Ruiyu Ni2018-01-241-12/+11
| | | | | | | | | | | | | | | | | | GetWakeupBuffer() tries to find a below-1M free memory, it checks whether the memory is allocated already in CheckOverlapWithAllocatedBuffer(). When there is a memory allocation hob (base = 0xff_00000000, size = 0x10000000), CheckOverlapWithAllocateBuffer() truncates the base to 0 which causes it always returns TRUE so GetWakeupBuffer() fails to find a below-1MB memory. The patch fixes this issue by using UINT64 type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
* UefiCpuPkg/CpuExceptionHandlerLib: alloc code memory for exception handlersJian J Wang2018-01-181-4/+14
| | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesData, EfiConventionalMemory, the BIOS will reset after timer initialized and started. The root cause is that the memory used to hold the exception and interrupt handler is allocated with type of EfiBootServicesData and marked as non-executable due to NX feature enabled. This patch fixes it by allocating EfiBootServicesCode type of memory for those handlers instead. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: split wake up buffer into two partsJian J Wang2018-01-188-49/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PcdDxeNxMemoryProtectionPolicy is set to enable protection for memory of EfiBootServicesCode, EfiConventionalMemory, the BIOS will hang at a page fault exception during MP initialization. The root cause is that the AP wake up buffer, which is below 1MB and used to hold both AP init code and data, is type of EfiConventionalMemory (not really allocated because of potential conflict with legacy code), and is marked as non-executable. During the transition from real address mode to long mode, the AP init code has to enable paging which will then cause itself a page fault exception because it's just running in non-executable memory. The solution is splitting AP wake up buffer into two part: lower part is still below 1MB and shared with legacy system, higher part is really allocated memory of BootServicesCode type. The init code in the memory below 1MB will not enable paging but just switch to protected mode and jump to higher memory, in which the init code will enable paging and switch to long mode. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Fix timer interrupt is disabled after SwitchBSPRuiyu Ni2018-01-181-0/+1
| | | | | | | | | | | | | | Commits a2ea6894e6ca95e8d7a254593661a79e4b988626 * UefiCpuPkg/MpInitLib: Fix a bug that AP enters timer INT handler masked the interrupts in AP. But it didn't unmask the interrupt in new BSP when Switch BSP happens. The patch fixed this issue. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com> Cc: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chainLiming Gao2018-01-165-22/+52
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=849 In V2, use "mov rax, strict qword 0" to replace the hard code db. 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chainLiming Gao2018-01-161-7/+20
| | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=849 In V2, use mov rax, strict qword 0 to replace the hard code db. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg: Enhance feature dependency checkSong, BinX2018-01-151-0/+3
| | | | | | | | | | Enhance MCA feature dependency check base on SDM pseudocode example 15-1. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: fix 32-bit build errorJian J Wang2018-01-111-1/+1
| | | | | | | | | | Cc: Dandan Bi <dandan.bi@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 01:01:52 +0000