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* UefiCpuPkg: Fix unchecked returns and potential integer overflowskenlautner6 days12-44/+339
| | | | | | | | | | | Resolves several issues in UefiCpuPkg related to: 1. Unchecked returns leading to potential NULL or uninitialized access. 2. Potential unchecked integer overflows. 3. Incorrect comparison between integers of different sizes. Co-authored-by: kenlautner <85201046+kenlautner@users.noreply.github.com> Signed-off-by: Chris Fernald <chfernal@microsoft.com>
* UefiCpuPkg: Use public Architectural MSRs from MdePkgVivian Nowka-Keane10 days5-24/+31
| | | | | | | Replaced local Msr defines with inclusion of Register/Amd/Msr.h in Amd libraries. Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com>
* UefiCpuPkg/MtrrLib: Fix unit test read overflowMichael D Kinney11 days1-1/+1
| | | | | | | Change conditional check to check the array index before reading the array member to prevent read past end of buffer. Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Remove AMD 32-bit SMRAM save state mapPhil Noh2024-11-013-157/+101
| | | | | | | | | | Per AMD64 Architecture Programmer's Manual Volume 2: System Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64 architecture does not use the legacy SMM state-save area format (Table 10-2) for 32-bit SMRAM save state map. Clean up codes for the invalid save state map. Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg/MmUnblockMemoryLib: Check if buffer range is validDun Tan2024-10-301-0/+90
| | | | | | | | | | | Check if input buffer range unblockable: 1.The input buffer range to block should be totally covered by one or multi memory allocation HOB 2.All the memory allocation HOB that overlap with the input buffer range should be EfiRuntimeServicesData, EfiACPIMemoryNVS or EfiReservedMemoryType. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: Add SmmCpuPlatformHookBeforeMmiHandlerJiaxin Wu2024-10-121-1/+19
| | | | | | | | | | | | | This patch is to add SmmCpuPlatformHookBeforeMmiHandler interface in SmmCpuPlatformHookLib. The new API can be used to perform the platform specific items before executing MMI Handler. For example, Intel can leverage this API to clear the pending SMI bit after all CPUs finish the sync and before the MMI handlers. If so, the the redundant SMI can be avoided after CPU exit from current SMI. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/MpLib: Remove NotifyOnS3SmmInitDonePpiZhiguang Liu2024-10-102-65/+0
| | | | | | | | | | | | | Previously, the SMM S3 resume code required taking control of APs to perform SMM rebase, which would overwrite the context set by MpLib. As a result, MpLib needed to wake up APs using InitSipiSipi to restore the context after SMM S3 resume. With the recent change where SMM rebase occurs in the early PEI phase, the SMM S3 resume code no longer modifies AP context. Therefore, the forced use of InitSipiSipi after SMM S3 resume is no longer necessary. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: RiscV64: initialize FPUHeinrich Schuchardt2024-10-042-0/+48
| | | | | | | | | | | | The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* UefiCpuPkg/MtrrLib: MtrrLibIsMtrrSupported always return FALSE in TD-GuestMin M Xu2024-09-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Currently, TDX exposes MTRR CPUID bit to TDX VM. So based on the CPUID, the guest software components (OVMF/TDVF and guest kernel) will access MTRR MSRs. One problem for guest to use of MTRR is the change of MTRR setting needs to set CR0.CD=1, which will case #VE for TDX. For Linux kernel, there is a mechanism called SW defined MTRR introduced by the patch https://lore.kernel.org/all/20230502120931. 20719-4-jgross@suse.com/. If this is integrated for TDX guest, then Linux kernel will not access any MTRR MSRs. So we update MtrrLibIsMtrrSupported() to always return false for TD-Guest, then TDVF will not access MTRR MSRs at all. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Binbin Wu <binbin.wu@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg/AmdSmmCpuFeaturesLib: Skip SMBASE configurationPhil Noh2024-09-172-5/+28
| | | | | | | | | This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg: Using the new name of LoongArch CSR 0x20 registerChao Li2024-08-302-2/+2
| | | | | | | | | | | Since the LoongArch SPEC has adjusted the CSR 0x20 register name and the MdePkg also added the new name, so enable it in UefiCpuPkg. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/MpInitLib: Skip X2APIC enabling when BSP in X2APIC alreadyRay Ni2024-08-281-1/+3
| | | | | | | | | | | The BSP's APIC mode is synced to all APs in CollectProcessorCount(). So, it's safe to skip the X2 APIC enabling in AutoEnableX2Apic() which runs later when BSP's APIC mode is X2 APIC already. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Sync BSP's APIC mode to APs in InitConfig pathRay Ni2024-08-282-5/+28
| | | | | | | | | | | | The change saves the BSP's initial APIC mode and syncs to all APs in first time wakeup. It allows certain platforms to switch to X2 APIC as early as possible and also independent on CpuFeaturePei/Dxe. The platform should switch BSP to X2 APIC mode first before the CpuMpPeim runs. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Separate X2APIC enabling to subfunctionRay Ni2024-08-281-23/+42
| | | | | | | | | | | | | | It's very confusing that auto X2 APIC enabling and APIC ID sorting are all performed inside CollectProcessorCount(). The change is to separate the X2 APIC enabling to AutoEnableX2Apic() and call that from MpInitLibInitialize(). SortApicId() is called from MpInitLibInitialize() as well. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Add MM Unblock Page Libraryxieyuanh2024-08-282-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | This library provides an interface to request non-MMRAM pages to be mapped/unblocked from inside MM environment. For MM modules that need to access areas outside of MMRAMs, the agents responsible for setting up these regions must use this API to enable access to these memory areas from within MM. During the IPL, when RestrictedMemoryAccess is enabled, this unblocked memory is specifically used to create a BuildResourceHob, which allocates storage for the SMM accessible DRAM (non-MMIO) range. Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Dun Tan <dun.tan@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg: CpuPageTableLibTestHost: Disable Random Test SuiteOliver Smith-Denny2024-08-271-7/+8
| | | | | | | | | | | | | Commit 2f499c36db51980ad43fc6b578c7678a1720bd9c commented out the RandomTestCase tests in CpuPageTableLibTestHost, but it left the test suite being registered without any tests. This causes a failure for tools that check to ensure tests are being registered with test suites. This patch comments out the test suite in addition to the tests being added to it. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg/MpInitLib: Reduce compiler dependencies for LoongArchDongyan Qian2024-07-251-2/+2
| | | | | | | | | | | | | | | Structure assignment may depend on the compiler to expand to memcpy. For this, we may need to add -mno-memcpy to the compilation flag. Here, we reduce dependencies and use CopyMem for data conversion without memcpy. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg: Removing redundant parameter in RestoreVolatileRegistersZhiguang Liu2024-07-241-25/+20
| | | | | | | | Given that the second parameter can be universally set to TRUE across all use cases, its removal simplifies the function interface and the associated code paths. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Change RestoreVolatileRegisters second parameterZhiguang Liu2024-07-241-4/+4
| | | | | | | | | | | | | | | | | | | Analysis of the current usage patterns revealed that this parameter should consistently set to TRUE. Specifically, the parameter was found to be False in the following scenarios: 1. During the initial volatile register setup for the first AP wake-up in both the PEI and DXE phases. In these instances, the volatile registers are pre-initialized in MpInitLibInitialize(), and manually setting them to zero does not require altering the DR state. 2. When switching the BSP, the new BSP does not synchronize the DR. This behavior is now adjusted to ensure the DR state is synchronized, aligning with a more logical and expected behavior when transitioning BSP roles. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Combine the code to set ApInitDoneZhiguang Liu2024-07-241-5/+1
| | | | | | | | | In previoud commit, we remove the ApInitReconfig status. Now there are only two status ApInitConfig and ApInitDone. Only the very first waking up AP needs to set ApInitConfig status. Therefore, if this is not the first wake up, set ApInitDone status Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Remove ApInitReconfig statusZhiguang Liu2024-07-242-18/+12
| | | | | | | | | | ApInitReconfig status is used to indicate that when AP wakes up, AP need to restore volatile registers from BSP and use InitSipiSipi. Since we handle the volatile registers well, we can use WakeUpByInitSipiSipi flag to replace ApInitReconfig. Avoid using ApInitReconfig can simplify code. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Let AP always save/restore volatile registersZhiguang Liu2024-07-241-46/+25
| | | | | | | | | | | | | | | | | | | | | | | | When enable stack guard, APs needs separate GDTs. In current code, APs will lose their separate GDTs when AP get disabled and later re-enabled. This is because when re-enabling AP, AP restores volatile registers from BSP. This patch updates the AP management to ensure that each AP saves and restores its own set of volatile registers to solve this issue. Key changes include: - APs now maintain their own volatile register space, eliminating dependency on the BSP's register state. - Special handling is implemented for the first AP wake-up during the PEI and DXE phases, where the volatile registers are synchronized from the BSP. - When switching BSP, remove manual handling the global variable CpuMpData->CpuData[Index].VolatileRegisters. The manually handling in previous code is because, old BSP may not save volatile registers after the AP procedure and new BSP's VolatileRegisters buffer may be used by other APs. Now, since AP always save/restore volatile registers from their own buffer, no need to do the special handling. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Sync the init timer count instead of current timer countZhiguang Liu2024-07-242-24/+29
| | | | | | | | | BSP should save and sync to AP the init timer count instead of current timer count. Also, BSP can check the init timer count to know if the local apic timer is enabled. Only sync the setting when it is enabled. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Preserve Local APIC Timer Settings During BSP SwitchZhiguang Liu2024-07-241-1/+6
| | | | | | | | | | | | | | | | | | | | | This update ensures the consistency of Local APIC timer settings across all processors when a BSP switch occurs. The Local APIC timer is utilized in two distinct scenarios: 1. As a delay mechanism within the timer library. 2. To generate periodic timer interrupts during the DXE phase. For scenario 1, APs can simply inherit the initial settings from the BSP. Even the local APIC timer setting is changed by BSP later, AP can still use the old setting. Therefore, the code to save the Local APIC timer can be moved to MpInitLibInitialize(). For scenario 2, because normal AP doesn't enable timer interrupt, we only need to care SwitchBsp case. It is crucial that the periodic timer interrupts remain operational after BSP is switched. To achieve this, the Local APIC timer settings on old BSP are now preserved and synced to new BSP. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Also exchange CPU_AP_DATA in SortApicId()Zhiguang Liu2024-07-241-14/+8
| | | | | | | | CPU_AP_DATA contains AP's information such as CpuHealthy and VolatileRegisters. Exchange the whole CPU_AP_DATA buffer instead some fields to make code more simple. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Add AMD SEV-ES features supportAlexey Kardashevskiy2024-07-041-3/+9
| | | | | | | | | | | | | | | | | | | | | | CONFIDENTIAL_COMPUTING_GUEST_ATTR is not a simple SEV level anymore and includes a feature mask since the previous commit. Fix AmdMemEncryptionAttrCheck to check the level and feature correctly and add DebugVirtualization support. Since the actual feature flag is not set yet, this should cause no behavioural change. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Alexey Kardashevskiy <aik@amd.com> --- Changes: v5: * "rb" from Tom
* UefiCpuPkg/Library: Add MM_STANDALONE type for SmmCpuPlatformHookLibJiaxin Wu2024-06-281-1/+1
| | | | | | | | | | | | Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/Library: Add MM_STANDALONE type for MmSaveStateLibJiaxin Wu2024-06-281-1/+1
| | | | | | | | | | | | Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/ExceptionHandler: Fix a context error in LoongArch64Dongyan Qian2024-06-261-0/+1
| | | | | | | | | | | | | On the LoongArch platform: the a0 register can be used as both a function parameter and a return value. Due to parameter EFI_SYSTEM_CONTEXT being overwritten by an invalid context address, when calling GetExceptionType, incorrect parameter address causes memory access exception. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4796 Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
* UefiCpuPkg: Correct the count of different type of Cache.xieyuanh2024-06-211-1/+2
| | | | | | | | | | | | | | | This patch fixes an error in calculating cache sizes for cores from different Dies. The original code incorrectly cleared cache sizes for different core types during intermediate calculation steps, leading to mistakes in counting duplicate entries. This patch adds a check for cache size to distinguish between different cache types. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: xieyuanh <yuanhao.xie@intel.com>
* UefiCpuPkg/MpInitLib: Update references to SEV-SNP header filePaul Grimes2024-06-184-4/+5
| | | | | | | | Update reference to SevSnpMsr.h as part of a refactor of MSR definitions and SEV-SNP related defines. Remove family-specific references (filename) as these defines are common to all modern EPYC Processors. Signed-off-by: Paul Grimes <paul.grimes@amd.com>
* UefiCpuPkg/SmmCpuSyncLib: Add MM_STANDALONE tag.xieyuanh2024-06-171-2/+2
| | | | | | | | | | | | | Declares in the .inf file that the current component is an MM_STANDALONE Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg:fix issue when splitting paging entryDun Tan2024-06-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix issue when splitting leaf paging entry in CpuPageTableLib code. In previous code, before we assign the new child paging structure address to the content of splitted paging entry, PageTableLibSetPnle() is called to make sure the bit7 is set to 0, which indicate the previous leaf entry is changed to non-leaf entry now. There is a gap between we change the bit7 and we assign the new child paging structure address to the content of the splitted paging entry. If the address of code execution or data access happens to be in the range covered by the splitted paging entry, this gap may cause issue. In this patch, we prepare the new paging entry content value in a local variable and assign the value to the splitted paging entry at once. The volatile keyword is used to ensure that no optimization will occur in compilation. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhou Jianfeng <jianfeng.zhou@intel.com>
* UefiCpuPkg:Relocate AP to new safe buffer in PeiMpLibDun Tan2024-06-043-2/+161
| | | | | | | | | | | | | | | | | | | | In this commit, change PeiMpLib to install callback of gEdkiiEndOfS3ResumeGuid to relocate AP to new safe buffer. The gEdkiiEndOfS3ResumeGuid is installed in S3Resume.c before jmping to OS waking vector. Previously, code in CpuS3.c of PiSmmCpuDxe driver will prepare the new safe buffer for AP and place AP in hlt loop state. With this code change, we can remove the Machine Instructions of mApHltLoopCode in PiSmmCpuDxe. Also we can reuse the related code in DxeMpLib for PeiMpLib. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg:Move some code in DxeMpLib to common placeDun Tan2024-06-043-148/+198
| | | | | | | | | | | | | | Move some code in DxeMpLib.C to common MpLib.c. The related code is to relocate Ap to new safe buffer before booting into OS. In next commits, these code also will be used by PeiMpLib. This commit doesn't change any code functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg:Abstract some DxeMpLib code to functionDun Tan2024-06-041-82/+140
| | | | | | | | | | | | | Abstract some DxeMpLib code to function in this commit. Some of these internal functions will be moved to common MpLib.c in following commits. Then PeiMpLib can reuse the code. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Disable PG in IA32 ApLoopCodeDun Tan2024-06-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | Disable paging in IA32 RelocateApLoop assembly code to fix the issue that the AP page table is unavailiable after boot OS under IA32 execution mode. This issue exist in IA32 PEI + IA32 DXE normal boot (also S3 boot with IA32 PEI after previous three commits are accepted). In current MpLib code, the IA32 execution mode code did not create page table in reserved memory like what X64 code did. If PcdCpuStackGuard is TRUE, the PG is enabled for AP in current RelocateApLoop assembly code. And the page table for AP is unavailiable after boot OS. This might cause potential issue. So disable PG in IA32 RelocateApLoop. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/MpLib:Do not assume BSP is #0.Ning Feng2024-05-271-18/+31
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4778 MPInitlib have wrong expectation that BSP index should always be 0 in MpInitLibInitialize(), SwitchBsp(),ApWakeupFunction(). That will cause the data mismatch, if the initial BSP is not 0. Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Ning Feng <ning.feng@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/Library: Support to get processor extended infoJiaxin Wu2024-05-082-4/+4
| | | | | | | | | | | | | | Intel has some features need to use processor extended information under CPU feature InitializeFunc(), so add code to support it: This patch is to add CPU_V2_EXTENDED_TOPOLOGY to get processor extended info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add library instance for AMDJiaxin Wu2024-05-082-0/+185
| | | | | | | | | | | | | | | | | | Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary CpuIndexJiaxin Wu2024-05-085-23/+3
| | | | | | | | | | | This patch is to remove unnecessary CpuIndex. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary global variableJiaxin Wu2024-05-081-56/+32
| | | | | | | | | | | | | | This patch aims on mProcessorInfo global variable, which can be defined as local variable in SmmRelocateBases(). With this patch, no need to allocate the memory for all CPUs to store the Processor Info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Avoid unnecessary memory allocationJiaxin Wu2024-05-081-111/+90
| | | | | | | | | | | | | | | | | Since SMM relocation is performed serially for each CPU, there is no need to allocate buffers for all CPUs to store the SmBase address in mSmBase and the Rebased flag in mRebased. A defined global variable is sufficient. This patch focuses on the mSmBase and mRebased global variables to prevent unnecessary memory allocation for these variables. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Rename global variablesJiaxin Wu2024-05-084-35/+35
| | | | | | | | | | | | | This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add SmmRelocationLib library instanceJiaxin Wu2024-05-088-0/+1395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch just separates the smbase relocation logic from PiSmmCpuDxeSmm driver, and moves to the SmmRelocationInit interface. It maintains the original implementation of most functions and leaves the definitions of global variables intact. Further refinements to the code are planned for subsequent patches. Platform shall consume the interface for the smbase relocation if need SMM support. Note: Before using SmmRelocationLib, the PiSmmCpuDxeSmm driver allocates the SMRAM to be used for SMI handler and Save state area of each processor from Smst->AllocatePages(). With SmmRelocationLib, the SMRAM allocation for SMI handlers and Save state areas is moved to early PEI phase (Smst->AllocatePages() service is not available). So, the allocation is done by splitting the SMRAM out of the SMRAM regions reported from gEfiSmmSMramMemoryGuid. So, Platform must produce the gEfiSmmSMramMemoryGuid HOB for SmmRelocationLib usage. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/Library: Cleanup debug message in LmceSupportJiaxin Wu2024-04-301-4/+1
| | | | | | | | | | | | | | | | ProcessorNumber 0 is not always BSP. Debug message based on 0 of ProcessorNumber is incorrect. This patch is to clean the debug message in LmceSupport directly. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Zeng Star <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: AP creation support under an SVSMTom Lendacky2024-04-171-9/+19
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 When running under an SVSM, the VMPL level of the APs that are started must match the VMPL level provided by the SVSM. Additionally, each AP must have a Calling Area for use with the SVSM protocol. Update the AP creation to properly support running under an SVSM. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
* UefiCpuPkg/MpInitLib: Use AmdSvsmSnpVmsaRmpAdjust() to set/clear VMSATom Lendacky2024-04-175-81/+9
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The RMPADJUST instruction is used to change the VMSA attribute of a page, but the VMSA attribute can only be changed when running at VMPL0. To prepare for running at a less priviledged VMPL, use the AmdSvsmLib library API to perform the RMPADJUST. The AmdSvsmLib library will perform the proper operation on behalf of the caller. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/AmdSvsmLib: Create the AmdSvsmLib library to support an SVSMTom Lendacky2024-04-173-0/+148
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 In order to support an SEV-SNP guest running under an SVSM at VMPL1 or lower, a new library must be created. This library includes an interface to detect if running under an SVSM, an interface to return the current VMPL, an interface to perform memory validation and an interface to set or clear the attribute that allows a page to be used as a VMSA. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Always use AP Create if GhcbApicIds HOB is presentTom Lendacky2024-04-176-13/+112
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 Currently, the first time an AP is started for an SEV-SNP guest, it relies on the VMSA as set by the hypervisor. If the list of APIC IDs has been retrieved, this is not necessary. The list of APIC IDs will be identified by a GUIDed HOB. If the GUIDed HOB is present, use the SEV-SNP AP Create protocol to start the AP for the first time and each time thereafter. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-21 14:47:16 +0000