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* UefiCpuPkg/Library: Support to get processor extended infoJiaxin Wu14 days2-4/+4
| | | | | | | | | | | | | | Intel has some features need to use processor extended information under CPU feature InitializeFunc(), so add code to support it: This patch is to add CPU_V2_EXTENDED_TOPOLOGY to get processor extended info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add library instance for AMDJiaxin Wu2024-05-082-0/+185
| | | | | | | | | | | | | | | | | | Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM Save State difference. Cc: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Cc: Abner Chang <abner.chang@amd.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary CpuIndexJiaxin Wu2024-05-085-23/+3
| | | | | | | | | | | This patch is to remove unnecessary CpuIndex. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Remove unnecessary global variableJiaxin Wu2024-05-081-56/+32
| | | | | | | | | | | | | | This patch aims on mProcessorInfo global variable, which can be defined as local variable in SmmRelocateBases(). With this patch, no need to allocate the memory for all CPUs to store the Processor Info. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Avoid unnecessary memory allocationJiaxin Wu2024-05-081-111/+90
| | | | | | | | | | | | | | | | | Since SMM relocation is performed serially for each CPU, there is no need to allocate buffers for all CPUs to store the SmBase address in mSmBase and the Rebased flag in mRebased. A defined global variable is sufficient. This patch focuses on the mSmBase and mRebased global variables to prevent unnecessary memory allocation for these variables. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Rename global variablesJiaxin Wu2024-05-084-35/+35
| | | | | | | | | | | | | This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/SmmRelocationLib: Add SmmRelocationLib library instanceJiaxin Wu2024-05-088-0/+1395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch just separates the smbase relocation logic from PiSmmCpuDxeSmm driver, and moves to the SmmRelocationInit interface. It maintains the original implementation of most functions and leaves the definitions of global variables intact. Further refinements to the code are planned for subsequent patches. Platform shall consume the interface for the smbase relocation if need SMM support. Note: Before using SmmRelocationLib, the PiSmmCpuDxeSmm driver allocates the SMRAM to be used for SMI handler and Save state area of each processor from Smst->AllocatePages(). With SmmRelocationLib, the SMRAM allocation for SMI handlers and Save state areas is moved to early PEI phase (Smst->AllocatePages() service is not available). So, the allocation is done by splitting the SMRAM out of the SMRAM regions reported from gEfiSmmSMramMemoryGuid. So, Platform must produce the gEfiSmmSMramMemoryGuid HOB for SmmRelocationLib usage. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/Library: Cleanup debug message in LmceSupportJiaxin Wu2024-04-301-4/+1
| | | | | | | | | | | | | | | | ProcessorNumber 0 is not always BSP. Debug message based on 0 of ProcessorNumber is incorrect. This patch is to clean the debug message in LmceSupport directly. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Zeng Star <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: AP creation support under an SVSMTom Lendacky2024-04-171-9/+19
| | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 When running under an SVSM, the VMPL level of the APs that are started must match the VMPL level provided by the SVSM. Additionally, each AP must have a Calling Area for use with the SVSM protocol. Update the AP creation to properly support running under an SVSM. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
* UefiCpuPkg/MpInitLib: Use AmdSvsmSnpVmsaRmpAdjust() to set/clear VMSATom Lendacky2024-04-175-81/+9
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 The RMPADJUST instruction is used to change the VMSA attribute of a page, but the VMSA attribute can only be changed when running at VMPL0. To prepare for running at a less priviledged VMPL, use the AmdSvsmLib library API to perform the RMPADJUST. The AmdSvsmLib library will perform the proper operation on behalf of the caller. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/AmdSvsmLib: Create the AmdSvsmLib library to support an SVSMTom Lendacky2024-04-173-0/+148
| | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 In order to support an SEV-SNP guest running under an SVSM at VMPL1 or lower, a new library must be created. This library includes an interface to detect if running under an SVSM, an interface to return the current VMPL, an interface to perform memory validation and an interface to set or clear the attribute that allows a page to be used as a VMSA. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Always use AP Create if GhcbApicIds HOB is presentTom Lendacky2024-04-176-13/+112
| | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4654 Currently, the first time an AP is started for an SEV-SNP guest, it relies on the VMSA as set by the hypervisor. If the list of APIC IDs has been retrieved, this is not necessary. The list of APIC IDs will be identified by a GUIDed HOB. If the GUIDed HOB is present, use the SEV-SNP AP Create protocol to start the AP for the first time and each time thereafter. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add multiprocessor library for LoongArch64Chao Li2024-04-166-12/+2871
| | | | | | | | | | | | | Added LoongArch multiprocessor initialization instance into MpInitLib. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add CpuMmuLib to UefiCpuPkgChao Li2024-04-168-0/+1005
| | | | | | | | | | | | | | | | | | Add a new base library named CpuMmuLib and add a LoongArch64 instance with in the library. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Xianglai Li <lixianglai@loongson.cn> Co-authored-by: Bibo Mao <maobibo@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add CPU exception library for LoongArchChao Li2024-04-168-9/+1273
| | | | | | | | | | | | | | Added LoongArch exception handler into CpuExceptionHandlerLib. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Add LoongArch64 CPU Timer instanceChao Li2024-04-162-2/+263
| | | | | | | | | | | | | | Add the LoongArch64 CPU Timer instance to CpuTimerLib, using CPUCFG 0x4 and 0x5 for Stable Counter frequency. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4734 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Reorder the INF files alphabeticallyChao Li2024-04-162-26/+28
| | | | | | | | | | | | | Some of the order is not in alphabetical, reorder. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Reorder the INF files alphabeticallyChao Li2024-04-164-32/+32
| | | | | | | | | | | | | Some of the order is not in alphabetical, reorder. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuTimerLib: Reorder the INF file alphabeticallyChao Li2024-04-161-1/+1
| | | | | | | | | | | | | Some of the order is not in alphabetical, reorder. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4726 Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Chao Li <lichao@loongson.cn> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: RISC-V: MMU: Support Svpbmt extensionTuan Phan2024-04-082-21/+86
| | | | | | | | | | | | The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be supported when Svpbmt extension available. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* UefiCpuPkg: RISC-V: MMU: Explictly use UINT64 instead of UINTNTuan Phan2024-04-081-82/+76
| | | | | | | | | | | | While UINTN defined for RISC-V 64 bits is UINT64, explictly using UINT64 for those variables that clearly are UINT64. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* UefiCpuPkg/CpuPageTableLib: qualify page table accesses as volatileZhou Jianfeng2024-03-011-18/+18
| | | | | | | | | | | | | | | | | | | | | Add volatile qualifier to page table related variable to prevent compiler from optimizing away the variables which may lead to unexpected result. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Cc: Zhang Di <di.zhang@intel.com> Cc: Tan Dun <dun.tan@intel.com> Cc: Michael Brown <mcb30@ipxe.org> Message-Id: <20240301025447.41170-1-jianfeng.zhou@intel.com> Reviewed-by: Michael Brown <mcb30@ipxe.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: reconstruct commit manually, from corrupt patch email on-list]
* UefiCpuPkg/CpuPageTableLib: Fix IN OUT parameters marked as INZhou Jianfeng2024-03-011-16/+16
| | | | | | | | | | | | | | | | | | | Some IN OUT parameters in CpuPageTableMap.c were mistakenly marked as IN. "IN" replaced with "IN OUT" in the following interfaces: PageTableLibSetPte4K(): Pte4K PageTableLibSetPleB(): PleB PageTableLibSetPle(): Ple PageTableLibSetPnle(): Pnle Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240222023922.29275-1-jianfeng.zhou@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: add struct MP_HAND_OFF_CONFIGGerd Hoffmann2024-02-294-22/+75
| | | | | | | | | | | | | | | | | | | | | | Move the WaitLoopExecutionMode and StartupSignalValue fields to a separate HOB with the new struct. WaitLoopExecutionMode and StartupSignalValue are independent of processor index ranges; they are global to MpInitLib (i.e., the entire system). Therefore they shouldn't be repeated in every MpHandOff GUID HOB. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240228114855.1615788-1-kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Oliver Steffen <osteffen@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> [lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list posting into "Cc:" tags in the commit message, in order to pacify "PatchCheck.py"]
* UefiCpuPkg/MpInitLib: return early in GetBspNumber()Gerd Hoffmann2024-02-261-7/+4
| | | | | | | | | | | | After finding the BSP Number return the result instead of continuing to loop over the remaining processors. Suggested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240222160106.686484-7-kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: s/ASSERT (FALSE)/ASSERT_EFI_ERROR (EFI_NOT_FOUND)/ [Ray]]
* UefiCpuPkg/MpInitLib: Add support for multiple HOBs to SaveCpuMpData()Gerd Hoffmann2024-02-261-18/+30
| | | | | | | | | | | Add support for splitting Hand-Off data into multiple HOBs. This is required for VMs with thousands of CPUs. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240222160106.686484-6-kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: define one local variable per line [Ray]]
* UefiCpuPkg/MpInitLib: Add support for multiple HOBs to MpInitLibInitializeGerd Hoffmann2024-02-261-21/+47
| | | | | | | | | | | | | | | Loop over all MP_HAND_OFF HOBs instead of expecting a single HOB covering all CPUs in the system. Add a new FirstMpHandOff variable, which caches the first HOB body for faster lookups. It is also used to check whenever MP_HAND_OFF HOBs are present. Using the MpHandOff pointer for that does not work any more because the variable will be NULL at the end of HOB loops. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Message-Id: <20240222160106.686484-5-kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: Add support for multiple HOBs to SwitchApContext()Gerd Hoffmann2024-02-262-13/+24
| | | | | | | | | | Rename the MpHandOff parameter to FirstMpHandOff. Add loops so the function inspects all HOBs present in the system. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240222160106.686484-4-kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Add support for multiple HOBs to GetBspNumber()Gerd Hoffmann2024-02-261-8/+15
| | | | | | | | | | Rename the MpHandOff parameter to FirstMpHandOff. Add a loop so the function inspects all HOBs present in the system. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240222160106.686484-3-kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Add support for multiple HOBs to GetMpHandOffHobGerd Hoffmann2024-02-262-10/+28
| | | | | | | | | | | | | Rename the function to GetNextMpHandOffHob(), add MP_HAND_OFF parameter. When called with NULL pointer return the body of the first HOB, otherwise return the next in the chain. Also add the function prototype to the MpLib.h header file. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240222160106.686484-2-kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Fix issue that IsModified is wrongly set in PageTableMapZhiguang Liu2024-02-221-5/+13
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4614 About the IsModified, current function doesn't consider that hardware also may change the pagetable. The issue is that in the first call of internal function PageTableLibMapInLevel, the function assume page table is not changed, and add ASSERT to check. But hardware may change the page table, which cause the ASSERT happens. Fix the issue by adding addtional condition to only check if the page table is changed when the software want to modify the page table. Also, add more comment to explain this behavior. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Crystal Lee <CrystalLee@ami.com.tw> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Enhance function header for PageTableMap()Zhiguang Liu2024-02-221-0/+1
| | | | | | | | | | | PageTableMap() only modifies the PageTable root pointer when creating from zero. Explicitly explain it in function header. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Reduce and optimize access to attributeZhou Jianfeng2024-02-061-33/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is to reduce and optimize access to attribute in CpuPageTableLib. Unreasonable writing to attribute of page table may leads to expection. The assembly code for C code Pnle->Bits.Present = Attribute->Bits.Present looks like: and dword [rcx], 0xfffffffe and eax, 0x1 or [rcx], eax In case Pnle->Bits.Present and Attribute->Bits.Present is 1, Pnle->Bits.Present will be set to 0 for short time(2 instructions) which is unexpected. If some other core is accessing the page, it may leads to expection. This change reduce and optimize access to attribute of page table, attribute of page table is set only when it need to be changed. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topologyAbdul Lateef Attar2024-01-312-2/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AMD's new extended topology. If processor supports CPUID 80000026 leaf then obtain the topology information using new method. Algorithm: if CPUID is AMD: then check for AMD's extended cpu tology leaf. if yes then extract cpu tology based on AMD programmer manual's instruction. else then fallback to existing topology function. endif endif Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com> Message-Id: <d93822d37fd25dafd32795758cf47263b432e102.1705549445.git.AbdulLateef.Attar@amd.com> Acked-by: Ray Ni <ray.ni@intel.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com>
* UefiCpuPkg: Check lower 24 bits of ProcessorNumberduntan2024-01-091-1/+4
| | | | | | | | | | | | | | | | | | | | | Check lower 24 bits of ProcessorNumber instead of the value of ProcessorNumber in the API MpInitLibGetProcessorInfo() of MpInitLibUp instance. Lower 24 bits of ProcessorNumber contains the actual processor number. The BIT24 of input ProcessorNumber might be set to indicate if the EXTENDED_PROCESSOR_INFORMATION will be retrived. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Min Xu <min.m.xu@intel.com> Message-Id: <20240108050804.1718-3-dun.tan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: set EXTENDED_PROCESSOR_INFORMATION to 0duntan2024-01-093-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Set EXTENDED_PROCESSOR_INFORMATION to 0 in API MpInitLibGetProcessorInfo() of MpInitLibUp. This commit use ZeroMem() to set all fileds in output EFI_PROCESSOR_INFORMATION to 0 before StatusFlag field is reassigned. Previously EXTENDED_PROCESSOR_INFORMATION in the API MpInitLibGetProcessorInfo() of MpInitLibUp is ignored. In PEI/DXE MpInitLib, EXTENDED_PROCESSOR_INFORMATION will be retrived when BIT24 of input ProcessorNumber is set. This commit can avoid garbage in the output structure in MpInitLibGetProcessorInfo() of MpInitLibUp. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Min Xu <min.m.xu@intel.com> Message-Id: <20240108050804.1718-2-dun.tan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Implements SmmCpuSyncLib library instanceJiaxin Wu2023-12-202-0/+686
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implements SmmCpuSyncLib Library instance. The instance refers the existing SMM CPU driver (PiSmmCpuDxeSmm) sync implementation and behavior: 1.Abstract Counter and Run semaphores into SmmCpuSyncCtx. 2.Abstract CPU arrival count operation to SmmCpuSyncGetArrivedCpuCount(), SmmCpuSyncCheckInCpu(), SmmCpuSyncCheckOutCpu(), SmmCpuSyncLockDoor(). Implementation is aligned with existing SMM CPU driver. 3. Abstract SMM CPU Sync flow to: BSP: SmmCpuSyncReleaseOneAp --> AP: SmmCpuSyncWaitForBsp BSP: SmmCpuSyncWaitForAPs <-- AP: SmmCpuSyncReleaseBsp Semaphores release & wait during sync flow is same as existing SMM CPU driver. 4.Same operation to Counter and Run semaphores by leverage the atomic compare exchange. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/BaseXApicLib: Fix CPUID_V2_EXTENDED_TOPOLOGY detectionWu, Jiaxin2023-12-081-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to complete 170d4ce8, sync the change to BaseXApicLib. Checking the max cpuid leaf is not enough to figure whenever CPUID_V2_EXTENDED_TOPOLOGY is supported. Intel SDM says: Software must detect the presence of CPUID leaf 1FH by verifying (a) the highest leaf index supported by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15:0] reports a non-zero value. The same is true for CPUID leaf 0BH. This patch adds the EBX check to GetProcessorLocation2ByApicId(). The patch also fixes the existing check in GetProcessorLocationByApicId() to be in line with the spec by looking at bits 15:0. The comments are updated with a quote from the Intel SDM. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Message-Id: <20231115111553.6592-2-jiaxin.wu@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuPageTableLib/TestCase: Refine test case for PAE paging.Zhiguang Liu2023-12-062-4/+34
| | | | | | | | | | | | Refine test case: 1. Check PAE paging reserved bits is zero. 2. Set stack as random value. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Init local variable before using it.Zhiguang Liu2023-12-061-3/+1
| | | | | | | | | | | | | The local variable OneOfPagingEntry is used before initialized, this may cause reserved bit in page table entry is set especially in PAE paging mode. The bug is random because it depends on the value in stack. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/MpInitLib: Copy SEV-ES save area pointer during APIC ID sortingTom Lendacky2023-11-281-1/+7
| | | | | | | | | | | | | | | | | With SEV-SNP, the SEV-ES save area for a vCPU should be unique to that vCPU. After commit 3323359a811a, the VMSA allocation was re-used, but when sorting the CPUs by APIC ID, the save area was not updated to follow the original CPU. Similar to the StartupApSignal address, the SevEsSaveArea address should be updated when sorting the CPUs. This does not cause an issue at this time because all APs are in HLT state and then are (re)started at the same time, with the same VMSA contents. However, this should be fixed to account for any change in future behavior. Fixes: 3323359a811a ("UefiCpuPkg/MpInitLib: Reuse VMSA allocation to ...") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Use AsmCpuidEx() for CPUID_EXTENDED_TOPOLOGY leafTom Lendacky2023-11-281-1/+8
| | | | | | | | | | | | | The CPUID_EXTENDED_TOPOLOGY CPUID leaf takes a subleaf as input when returning CPUID information. However, the AsmCpuid() function does not zero out ECX before the CPUID instruction, so the input leaf is used as the sub-leaf for the CPUID request and returns erroneous/invalid CPUID data, since the intent of the request was to get data related to sub-leaf 0. Instead, use AsmCpuidEx() for the CPUID_EXTENDED_TOPOLOGY leaf. Fixes: d4d7c9ad5fe5 ("UefiCpuPkg/MpInitLib: use BSP to do extended ...") Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Update the comments of _CPU_MP_DATA.xieyuanh2023-11-272-6/+9
| | | | | | | | | | | | | | | | | | | | No functional changes in this patch. Updates the comments of _CPU_MP_DATA to delcared that duplications in CpuMpData are present to avoid to be direct accessed and comprehended in assembly code. CpuMpData: Intended for use in C code while ExchangeInfo are used in assembly code in this module. This patch deletes the unnecessary comments in CpuMpData, since CpuMpData is no longer responsible for passing information from PEI to DXE. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Laszlo Ersek lersek@redhat.com Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Enable execute disable bit.Yuanhao Xie2023-11-272-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch synchronizes the No-Execute bit in the IA32_EFER register for the APs before the RestoreVolatileRegisters operation. The commit 964a4f0, titled "Eliminate the second INIT-SIPI-SIPI sequence," replaces the second INIT-SIPI-SIPI sequence with the BSP calling the SwitchApContext function to initiate a specialized start-up signal, waking up APs in the DXE instead of using INIT-SIPI-SIPI. Due to this change, the logic for "Enable execute disable bit" in MpFuncs.nasm is no longer executed. However, to ensure the proper setup of the page table, it is necessary to synchronize the IA32_EFER.NXE for APs before executing RestoreVolatileRegisters . Based on SDM: If IA32_EFER.NXE is set to 1, it signifies execute-disable, meaning instruction fetches are not allowed from the 4-KByte page controlled by this entry. Conversely, if it is set to 0, it is reserved. Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek lersek@redhat.com Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Correct file description for MpHandOff header fileYuanhao Xie2023-10-311-1/+4
| | | | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Message-Id: <20231007063203.936-1-yuanhao.xie@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Rahul R Kumar <rahul.r.kumar@intel.com>
* UefiCpuPkg/MpInitLib: Wait for all APs to finish initializationYuanhao Xie2023-10-261-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aim: - To solve the assertion that checks if CpuMpData->FinishedCount equals (CpuMpData->CpuCount - 1). The assertion arises from a timing discrepancy between the BSP's completion of startup signal checks and the APs' incrementation of the FinishedCount. - This patch also ensures that "finished" reporting from the APs is as later as possible. More specifially: In the SwitchApContext() function, the BSP trigers the startup signal and check whether the APs have received it. After completing this check, the BSP then verifies if the FinishedCount is equal to CpuCount-1. On the AP side, upon receiving the startup signal, they invoke SwitchContextPerAp() and increase the FinishedCount to indicate their activation. However, even when all APs have received the startup signal, they might not have finished incrementing the FinishedCount. This timing gap results in the triggering of the assertion. Solution: Instead of assertion, use while loop to waits until all the APs have incremented the FinishedCount. Fixes: 964a4f032dcd Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <20231025114216.2824-1-yuanhao.xie@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/BaseXApicX2ApicLib: fix CPUID_V2_EXTENDED_TOPOLOGY detectionGerd Hoffmann2023-10-251-5/+16
| | | | | | | | | | | | | | | | | | | | | Checking the max cpuid leaf is not enough to figure whenever CPUID_V2_EXTENDED_TOPOLOGY is supported. Intel SDM says: Software must detect the presence of CPUID leaf 1FH by verifying (a) the highest leaf index supported by CPUID is >= 1FH, and (b) CPUID.1FH:EBX[15:0] reports a non-zero value. The same is true for CPUID leaf 0BH. This patch adds the EBX check to GetProcessorLocation2ByApicId(). The patch also fixes the existing check in GetProcessorLocationByApicId() to be in line with the spec by looking at bits 15:0. The comments are updated with a quote from the Intel SDM. Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2241388 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20231017112807.1244254-1-kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP modeTuan Phan2023-10-172-1/+8
| | | | | | | | | | | Introduce a PCD to control the maximum SATP mode that MMU allowed to use. This PCD helps RISC-V platform set bare or minimum SATP mode during bring up to debug memory map issue. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
* UefiCpuPkg/MtrrUnitTest: Add Unit test of setting/getting memoryYuanhaoXie2023-10-091-6/+36
| | | | | | | | | | | | | | | | attributes Add Unit test of trrGetMemoryAttributesInMtrrSettings and MtrrSetMemoryAttributesInMtrrSettings. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MtrrLib: Improve MtrrDebugPrintAllMtrrsWorker.YuanhaoXie2023-10-091-35/+10
| | | | | | | | | | | | | Improve MtrrDebugPrintAllMtrrsWorker by making use of MtrrGetMemoryAttributesInMtrrSettings. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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