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path: root/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
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* UefiCpuPkg: SmmProfile: Use public Architectural MSRs from MdePkgVivian Nowka-Keane7 days1-11/+4
| | | | | | Replaced local Msr defines with inclusion of Register/Amd/Msr.h. Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refactor code to create default Page TableJiaxin Wu2024-08-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For MM: Since all accessible NON-MMRAM memory and attribute shall be in ResourceDescriptor HOBs for MM, the page table for MM can be finalized and created in the default Page. For SMM: There are still 2 steps for the finalized default Page: 1. Create default Page 2. update the page table in the first SMI when SMM ready to lock happen This patch to refactor the GenSmmPageTable() function to create the default Page Table for Both SMM and MM: 1. Create NonMmram MemoryRegion 2. Gen NonMmram MemoryRegion PageTable 3. Gen MMRAM Range PageTable 4. Consider PcdCpuSmmStackGuard & PcdNullPointerDetectionPropertyMask cases. Meanwhile, mXdSupported needs to be initialized before GenSmmPageTable since it's required by GenSmmPageTable function. So, move the mXdSupported init from CheckFeatureSupported to the common EntryPoint function. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Move GetSmiCommandPort into DxeSmm CodeJiaxin Wu2024-08-281-2/+0
| | | | | | | | | | | | | | | | MM can not call the EfiLocateFirstAcpiTable(), so, move the function into DxeSmm Code. This will make InitSmmProfileCallBack() to be common function for both SMM and MM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg: rename and simplify IsAddressValid functionDun Tan2024-08-051-6/+9
| | | | | | | | | | | | | | | In this commit, we rename IsAddressValid function to IsSmmProfilePFAddressAbove4GValid and remove unneeded code logic in it. Currently, IsAddressValid is only used in the function RestorePageTableAbove4G. It's used to identify if a SMM profile PF address above 4G is inside mProtectionMemRange or not. So we can remove the PcdCpuSmmProfileEnable FALSE condition related code logic in it. Also the function name is change to be more detailed and specific. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg: rename the SmiDefaultPFHandler functionDun Tan2024-08-051-2/+2
| | | | | | | | Rename SmiDefaultPFHandler to SmiProfileMapPFAddress and move the implementation to SmmProfileArch.c since it only will be used when SMM profile is enabled. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid use global variable in InitSmmS3Cr3Jiaxin Wu2024-08-021-6/+5
| | | | | | | This patch is to avoid use global variable in InitSmmS3Cr3. No function impact. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check PDE entry exist or not before useJiaxin Wu2024-08-021-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the commit 701b5797 & 4ceefd6d, 2MB-page will be created to cover [0: 4G] by default if SmmProfile enabled, and it will be go through to change 2MB-page into 4KB-page during page table update (InitPaging). If so, there was no problem to assert PDE entry exist in the RestorePageTableBelow4G. But after above commits, PageTableMap API is used to create/update the page table, 1G-page will be the default page table mode, and only covers the limited address range. Those not covered ranges will be marked as non-present in 1g-page level address. If so, 2M-page address might not exist, it's incorrect to assert PDE entry exist in the RestorePageTableBelow4G. The correct behavior should check PDE entry exist or not, if not, PDE should be allocated and assigned to PDPTE. Note: RestorePageTableBelow4G () does not use 1G page size entries for the creation of new pages, maintaining consistency with the behavior of the original code. The purpose of this patch is to ensure that a Page Directory Entry (PDE) exists prior to its usage. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Remove UefiCpuLib from module INFs.Yu Pu2023-03-101-1/+0
| | | | | | | | | | | Because UefiCpuPkg/UefiCpuLib is merged to MdePkg/CpuLib, remove the dependency of UefiCpuLib. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Yu Pu <yu.pu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Apply uncrustify changesMichael Kubacki2021-12-071-50/+50
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMDKirkendall, Garrett2020-07-071-0/+3
| | | | | | | | | | | | | | | | AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register causes and exception on AMD processors. If Execution Disable is supported, but if the processor is an AMD processor, skip manipulating MSR_IA32_MISC_ENABLE[34] XD Disable bit. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Message-Id: <20200622131825.1352-5-Garrett.Kirkendall@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Use new EfiLocateFirstAcpiTable()Star Zeng2018-09-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=967 Request to add a library function for GetAcpiTable() in order to get ACPI table using signature as input. After evaluation, we found there are many duplicated code to find ACPI table by signature in different modules. This patch updates PiSmmCpuDxeSmm to use new EfiLocateFirstAcpiTable() and remove the duplicated code. Cc: Younas khan <pmdyounaskhan786@gmail.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Remove redundant library classes, Ppis and GUIDsshenglei2018-09-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some redundant library classes Ppis and GUIDs have been removed in inf, .c and .h files. v2: 1.Remove ReadOnlyVariable2.h in S3Resume.c which should be deleted in last version in which gEfiPeiReadOnlyVariable2PpiGuid was removed. 2.Remove the library class BaseLib in CpuPageTable.c which is included elsewhere. 3.Add library classes in SecCore.inf which are removed at last version. They are DebugAgentLib and CpuExceptionHandlerLib. 4.Add two Ppis in SecCore.inf which are removed at last version. They are gEfiSecPlatformInformationPpiGuid and gEfiSecPlatformInformation2PpiGuid. https://bugzilla.tianocore.org/show_bug.cgi?id=1043 https://bugzilla.tianocore.org/show_bug.cgi?id=1013 https://bugzilla.tianocore.org/show_bug.cgi?id=1032 https://bugzilla.tianocore.org/show_bug.cgi?id=1016 Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMMJian J Wang2018-08-301-0/+6
| | | | | | | | | | | | | | Since SMM profile feature has already implemented non-stop mode if #PF occurred, this patch just makes use of the existing implementation to accommodate heap guard and NULL pointer detection feature. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: patch "XdSupported" with PatchInstructionX86()Laszlo Ersek2018-04-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "mXdSupported" is a global BOOLEAN variable, initialized to TRUE. The CheckFeatureSupported() function is executed on all processors (not concurrently though), called from SmmInitHandler(). If XD support is found to be missing on any CPU, then "mXdSupported" is set to FALSE, and further processors omit the check. Afterwards, "mXdSupported" is read by several assembly and C code locations. The tricky part is *where* "mXdSupported" is allocated (defined): - Before commit 717fb60443fb ("UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.", 2016-11-17), it used to be a normal global variable, defined (allocated) in "SmmProfile.c". - With said commit, we moved the definition (allocation) of "mXdSupported" into "SmiEntry.nasm". The variable was defined over the last byte of a "mov al, 1" instruction, so that setting it to FALSE in CheckFeatureSupported() would patch the instruction to "mov al, 0". The subsequent conditional jump would change behavior, plus all further read references to "mXdSupported" (in C and assembly code) would read back the source (imm8) operand of the patched MOV instruction as data. This trick required that the MOV instruction be encoded with DB. In order to get rid of the DB, we have to split both roles: we need a label for the code patching, and "mXdSupported" has to be defined (allocated) independently of the code patching. Of course, their values must always remain in sync. (1) Reinstate the "mXdSupported" definition and initialization in "SmmProfile.c" from before commit 717fb60443fb. Change the assembly language definition ("global") to a declaration ("extern"). (2) Define the "gPatchXdSupported" label (type X86_ASSEMBLY_PATCH_LABEL) in "SmiEntry.nasm", and add the C-language declaration to "SmmProfileInternal.h". Replace the DB with the MOV mnemonic (keeping the imm8 source operand with value 1). (3) In CheckFeatureSupported(), whenever "mXdSupported" is set to FALSE, patch the assembly code in sync, with PatchInstructionX86(). Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Consume new APIsJeff Fan2017-04-071-5/+1
| | | | | | | | | | | | Consuming PeCoffSerachImageBase() from PeCoffGetEntrypointLib and consuming DumpCpuContext() from CpuExceptionHandlerLib to replace its own implementation. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRsJeff Fan2016-05-161-4/+1
| | | | | | | | | | | | | | BTS used DS save area by IA32_DS_AREA MSR to get invoker IP instead of the Last Branch Record Stack. So, removed the unnecessary BTS MSRs. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 filesMichael Kinney2015-10-191-0/+172
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module Changes between [PATCH v1] and [PATCH v2]: 1) Swap PTE init order for QEMU compatibility. Current PTE initialization algorithm works on HW but breaks QEMU emulator. Update the PTE initialization order to be compatible with both. 2) Update comment block that describes 32KB SMBASE alignment requirement to match contents of Intel(R) 64 and IA-32 Architectures Software Developer's Manual 3) Remove BUGBUG comment and call to ClearSmi() that is not required. SMI should be cleared by root SMI handler. [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> [pbonzini@redhat.com: InitPaging: prepare PT before filling in PDE] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18645 6f19259b-4bc3-4df7-8a09-765794883524
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