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* UefiCpuPkg/MtrrLib: Fix unit test read overflowMichael D Kinney2024-11-111-1/+1
| | | | | | | Change conditional check to check the array index before reading the array member to prevent read past end of buffer. Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/SecCore: Consume PcdMaxMappingAddressBeforeTempRamExitJiaxin Wu2024-11-073-81/+126
| | | | | | | | | | | Consume PcdMaxMappingAddressBeforeTempRamExit for page table creation in permanent memory before Temp Ram Exit. This patch will create the full page table in two steps: Step 1: Create the max address in page table before the Temporary RAM exit. Step 2: Create the full range page table after the Temporary RAM exit. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/UefiCpuPkg.dec: Add PcdMaxMappingAddressBeforeTempRamExitJiaxin Wu2024-11-071-0/+8
| | | | | | | | | | | | | | | This change is made for boot performance considerations. Before the Temporary RAM is disabled, the permanent memory is in UC state, causing the creation of the page table in permanent memory to take more time with larger page table sizes. Therefore, this patch adds the PcdMaxMappingAddressBeforeTempRamExit to provide the platform with the capability to control the max mapping address in page table before Temp Ram Exit. The value of 0xFFFFFFFFFFFFFFFF, then firmware will map entire physical address space. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Remove AMD 32-bit SMRAM save state mapPhil Noh2024-11-013-157/+101
| | | | | | | | | | Per AMD64 Architecture Programmer's Manual Volume 2: System Programming - 10.2.3 SMRAM State-Save Area (Rev 24593), the AMD64 architecture does not use the legacy SMM state-save area format (Table 10-2) for 32-bit SMRAM save state map. Clean up codes for the invalid save state map. Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg/MmUnblockMemoryLib: Check if buffer range is validDun Tan2024-10-301-0/+90
| | | | | | | | | | | Check if input buffer range unblockable: 1.The input buffer range to block should be totally covered by one or multi memory allocation HOB 2.All the memory allocation HOB that overlap with the input buffer range should be EfiRuntimeServicesData, EfiACPIMemoryNVS or EfiReservedMemoryType. Signed-off-by: Dun Tan <dun.tan@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix extraneous parenthesesMike Beaton2024-10-291-1/+1
| | | | | | | | | | | Without this change, when building OvmfPkg with -D SMM_REQUIRE using the XCODE5 toolchain we get: error: equality comparison with extraneous parentheses which stops the build. Signed-off-by: Mike Beaton <mjsbeaton@gmail.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Save and restore CR2 only if SmiProfile enableJiaxin Wu2024-10-161-2/+18
| | | | | | | | A page fault (#PF) that triggers an update to the page table only occurs if SmiProfile is enabled. Therefore, it is necessary to save and restore the CR2 register if SmiProfile is configured to be enabled. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Consume SmmCpuPlatformHookBeforeMmiHandler funcJiaxin Wu2024-10-121-8/+23
| | | | | | | | | | | | | This patch is for PiSmmCpuDxeSmm driver to add one round wait/release sync for BSP and AP to perform the SMM CPU Platform Hook before executing MMI Handler: SmmCpuPlatformHookBeforeMmiHandler (). With the function, SMM CPU driver can perform the platform specific items after one round BSP and AP sync (to make sure all APs in SMI) and before the MMI handlers. After the change, steps #1 and #2 are additional requirements if the MmCpuSyncModeTradition mode is selected. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg: Add SmmCpuPlatformHookBeforeMmiHandlerJiaxin Wu2024-10-122-2/+35
| | | | | | | | | | | | | This patch is to add SmmCpuPlatformHookBeforeMmiHandler interface in SmmCpuPlatformHookLib. The new API can be used to perform the platform specific items before executing MMI Handler. For example, Intel can leverage this API to clear the pending SMI bit after all CPUs finish the sync and before the MMI handlers. If so, the the redundant SMI can be avoided after CPU exit from current SMI. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clarification for BSP & APs Sync FlowJiaxin Wu2024-10-121-22/+22
| | | | | | | | | | | | | | | | | | | | This patch does not impact functionality. It aims to clarify the synchronization flow between the BSP and APs to enhance code readability and understanding: Steps #6 and #11 are the basic synchronization requirements for all cases. Steps #1 is additional requirements if the MmCpuSyncModeTradition mode is selected. Steps #1, #2, #3, #4, #5, #7, #8, #9, and #10 are additional requirements if the system needs to configure the MTRR. Steps #9 and #10 are additional requirements if the system needs to support the mSmmDebugAgentSupport. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/MpLib: Remove NotifyOnS3SmmInitDonePpiZhiguang Liu2024-10-102-65/+0
| | | | | | | | | | | | | Previously, the SMM S3 resume code required taking control of APs to perform SMM rebase, which would overwrite the context set by MpLib. As a result, MpLib needed to wake up APs using InitSipiSipi to restore the context after SMM S3 resume. With the recent change where SMM rebase occurs in the early PEI phase, the SMM S3 resume code no longer modifies AP context. Therefore, the forced use of InitSipiSipi after SMM S3 resume is no longer necessary. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/S3: Skip CR3 modification in S3Resume for 64-bit PEIZhiguang Liu2024-10-101-3/+5
| | | | | | | | | | | | | | | | Previously, when PEI was 32-bit and DXE was 64-bit, S3 resume code had to set or change the CR3 register before executing 64-bit code. However, with both PEI and DXE now may being 64-bit, this modification is unnecessary as PEI already utilizes sufficiently large page tables. Additionally, there is a bug in the current implementation where the changed CR3 during S3 resume could map only below 4G MMIO, which could lead to issues if end of PEI notify attempts to access above 4G. Overall, skipping the CR3 modification in S3Resume when PEI is 64-bit can fix the bug and also avoid unnecessary logic. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: RiscV64: initialize FPUHeinrich Schuchardt2024-10-048-0/+80
| | | | | | | | | | | | The OpenSSL library uses floating point registers. The is no guarantee that a prior firmware stage has enabled the FPU. Provide a library BaseRiscVFpuLib to * Enable the FPU and set it to state 'dirty'. * Clear the fcsr CSR. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* UefiCpuPkg/MtrrLib: MtrrLibIsMtrrSupported always return FALSE in TD-GuestMin M Xu2024-09-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Currently, TDX exposes MTRR CPUID bit to TDX VM. So based on the CPUID, the guest software components (OVMF/TDVF and guest kernel) will access MTRR MSRs. One problem for guest to use of MTRR is the change of MTRR setting needs to set CR0.CD=1, which will case #VE for TDX. For Linux kernel, there is a mechanism called SW defined MTRR introduced by the patch https://lore.kernel.org/all/20230502120931. 20719-4-jgross@suse.com/. If this is integrated for TDX guest, then Linux kernel will not access any MTRR MSRs. So we update MtrrLibIsMtrrSupported() to always return false for TD-Guest, then TDVF will not access MTRR MSRs at all. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Binbin Wu <binbin.wu@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
* UefiCpuPkg/AmdSmmCpuFeaturesLib: Skip SMBASE configurationPhil Noh2024-09-172-5/+28
| | | | | | | | | This patch is to avoid configure SMBASE if SmBase relocation has been done. If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. No need to do the relocation in SmmCpuFeaturesInitializeProcessor(). Signed-off-by: Phil Noh <Phil.Noh@amd.com>
* UefiCpuPkg: Add StackCheckLibOliver Smith-Denny2024-09-131-2/+8
| | | | | | | SecCore and SecCoreNative require StackCheckLib and so the NULL instance is linked against them here. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Remove RestrictedMemoryAccess check for MM CPUJiaxin Wu2024-09-066-31/+46
| | | | | | | | | | | | | | The PcdCpuSmmRestrictedMemoryAccess is declared as either a dynamic or fixed PCD. It is not recommended for use in the MM CPU driver. Furthermore, IsRestrictedMemoryAccess() is only needed for SMM. Therefor, there is no need for MM to consume the PcdCpuSmmRestrictedMemoryAccess. So, this patch is to add the SMM specific file for its own functions, with the change, the dependency of the MM CPU driver on PcdCpuSmmRestrictedMemoryAccess can be removed. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Clean mCpuSmmRestrictedMemoryAccessJiaxin Wu2024-09-061-7/+4
| | | | | | | | | | Currently, mCpuSmmRestrictedMemoryAccess is only used by the IsRestrictedMemoryAccess(). And IsRestrictedMemoryAccess() can consume the PcdCpuSmmRestrictedMemoryAccess directly. Therefore, mCpuSmmRestrictedMemoryAccess can be cleaned to simply the code logic. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Update IfReadOnlyPageTableNeededJiaxin Wu2024-09-061-18/+1
| | | | | | | | | | After the 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. If so, SMM PageTable Attributes can be set to ready-only since there is no need to update it. So, this patch is to remove restricted memory access check when setting the SMM PageTable attributes. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Correct SetPageTableAttributes func usageJiaxin Wu2024-09-062-12/+8
| | | | | | | | | | | SetPageTableAttributes() will use the IfReadOnlyPageTableNeeded() to determine whether it is necessary to set the page table itself to read-only. And IfReadOnlyPageTableNeeded() has already token into account the status of IsRestrictedMemoryAccess(). Therefore, there is no need for an additional call to IsRestrictedMemoryAccess() before calling the SetPageTableAttributes(). Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Deadloop if PFAddr is not supported by systemJiaxin Wu2024-09-061-1/+1
| | | | | | | Deadloop if PFAddr is not supported by system, no need check SMM CPU RestrictedMemory access enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Always save and restore CR2Jiaxin Wu2024-09-061-14/+4
| | | | | | | | | | | | | | | | | Following the commit 9f29fbd3, full mapping SMM page table is always created regardless the value of the PcdCpuSmmRestrictedMemoryAccess. Consequently, a page fault (#PF) that triggers an update to the page table occurs only when SmiProfile is enabled. Therefore, it is necessary to save and restore the CR2 register when SmiProfile is configured to be enabled. And the operation of saving and restoring CR2 is considered to be not heavy operation compared to the saving and restoring of CR3. As a result, the condition check for SmiProfile has been removed, and CR2 is now saved and restored unconditionally, without the need for additional condition checks. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix IsSmmCommBufferForbiddenAddress checkJiaxin Wu2024-09-062-1/+5
| | | | | | | | | | | | | | | | SmiPFHandler depends on the IsSmmCommBufferForbiddenAddress() to do the forbidden address check: For SMM, verifying whether an address is forbidden is necessary only when RestrictedMemoryAccess is enabled. For MM, all accessible address is recorded in the ResourceDescriptor HOB, so no need check the RestrictedMemoryAccess is enabled or not. This patch is to move RestrictedMemoryAccess check into SMM IsSmmCommBufferForbiddenAddress to align with above behavior. With the change, SmiPFHandler doesn't need to check the RestrictedMemoryAccess enable or not. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid to access MCA_CAP if CPU does not supportJiaxin Wu2024-09-061-5/+3
| | | | | | Do not access MCA_CAP MSR unless the CPU supports the SmmRegFeatureControl Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
* UefiCpuPkg/UefiCpuPkg.ci.yaml: Add PrEval CI configJoey Vagedes2024-09-021-0/+3
| | | | | | | | | | | Adds an entry to the package's CI configuration file that enable policy 5 for stuart_pr_eval. With this Policy, all INFs used by the package are extracted from the provided DSC file and compared against the list of changed *.inf (INF) files in the PR. If there is a match, stuart_pr_eval will specify that this package is affected by the PR and needs to be tested. Signed-off-by: Joey Vagedes <joey.vagedes@gmail.com>
* UefiCpuPkg: Using the new name of LoongArch CSR 0x20 registerChao Li2024-08-302-2/+2
| | | | | | | | | | | Since the LoongArch SPEC has adjusted the CSR 0x20 register name and the MdePkg also added the new name, so enable it in UefiCpuPkg. Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jiaxin Wu <jiaxin.wu@intel.com> Signed-off-by: Chao Li <lichao@loongson.cn>
* UefiCpuPkg/MpInitLib: Skip X2APIC enabling when BSP in X2APIC alreadyRay Ni2024-08-281-1/+3
| | | | | | | | | | | The BSP's APIC mode is synced to all APs in CollectProcessorCount(). So, it's safe to skip the X2 APIC enabling in AutoEnableX2Apic() which runs later when BSP's APIC mode is X2 APIC already. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Sync BSP's APIC mode to APs in InitConfig pathRay Ni2024-08-282-5/+28
| | | | | | | | | | | | The change saves the BSP's initial APIC mode and syncs to all APs in first time wakeup. It allows certain platforms to switch to X2 APIC as early as possible and also independent on CpuFeaturePei/Dxe. The platform should switch BSP to X2 APIC mode first before the CpuMpPeim runs. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/MpInitLib: Separate X2APIC enabling to subfunctionRay Ni2024-08-281-23/+42
| | | | | | | | | | | | | | It's very confusing that auto X2 APIC enabling and APIC ID sorting are all performed inside CollectProcessorCount(). The change is to separate the X2 APIC enabling to AutoEnableX2Apic() and call that from MpInitLibInitialize(). SortApicId() is called from MpInitLibInitialize() as well. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/UefiCpuPkg.dsc: Include PiSmmCpuStandaloneMm and required LibsJiaxin Wu2024-08-281-2/+8
| | | | | | | | | | | | Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Simplify SMM Profile Size CalculationJiaxin Wu2024-08-284-11/+11
| | | | | | | | | | | | | | | | | | | | | | The motivation of this change is to simplify the logic in StandaloneMmIpl when allocating the memory for SMM profile data. IPL does not need to detect the CPU feature regarding MSR DS Area. That change requires the PCD value contains the MSR DS Area. So, the size of SmmProfileData will be simplified to the PcdCpuSmmProfileSize directly. mMsrDsAreaSize will be within the PcdCpuSmmProfileSize if mBtsSupported is TRUE. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Avoid PcdCpuSmmProfileEnable check in MMJiaxin Wu2024-08-2812-17/+83
| | | | | | | | | | | | | | | | | | | | | | For MM, gMmProfileDataHobGuid Memory Allocation HOB is defined to indicate SMM profile feature enabled or not. If the HOB exist, SMM profile base address and size will be returned in the HOB, so no need to consume the PcdCpuSmmProfileEnable feature PCD to check enable or disable. To achieve above purpose, Add the IsSmmProfileEnabled () function. With this change, Both MM and SMM can use the new function for SMM profile feature check. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Cleanup SMM_CPU_SYNC_MODEJiaxin Wu2024-08-284-30/+24
| | | | | | | | | | | | | | | Use MM_CPU_SYNC_MODE instead of SMM_CPU_SYNC_MODE. Cleanup the duplicate definition. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refine DxeSmm PageTable update logicJiaxin Wu2024-08-285-144/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to refine the updatePageTable logic for DxeSmm. For DxeSmm, PageTable will be updated in the first SMI when SMM ready to lock happen: IF SMM Profile is TRUE: 1. Mark mProtectionMemRange attribute: SmrrBase:Present, SMM profile base:Present&Nx, MMRAM ranges:Present, MMIO ranges: Present&Nx. 2. Mark the ranges not in mProtectionMemRange as RP (non-present). IF SMM Profile is FALSE: 1. Mark Non-MMRAM ranges as NX. 2. IF RestrictedMemoryAccess is TRUE: Forbidden Address mark as RP (IsUefiPageNotPresent is TRUE). Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add PiSmmCpuStandaloneMm.infJiaxin Wu2024-08-281-0/+136
| | | | | | | | | | | | | | | This patch is to add PiSmmCpuStandaloneMm.inf for MM CPU support. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Check logging PF address for MMJiaxin Wu2024-08-284-0/+70
| | | | | | | | | | | | | | | This patch is to make sure only logging PF address for MM can run into the SmmProfilePFHandler. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Start SMM Profile early for MMJiaxin Wu2024-08-284-5/+24
| | | | | | | | | | | | | | | | SMM Profile start can be started early in SMM CPU EntryPoint since page table for SMM profile is ready. No need wait smm ready to lock. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Differentiate PerformRemainingTasksJiaxin Wu2024-08-285-103/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | For MM: SMRAM & PageTable itself & SMM Paging State shall be configured once the gEdkiiPiMmMemoryAttributesTableGuid is installed by SMM core. It will happen after MmIpl.Entrypoint. PerformRemainingTasks will be called before MmIpl.Entrypoint exit. For SMM: SMRAM & PageTable itself & SMM Paging State are still configured in the first SMI when SMM ready to lock happen. So, this patch is to differentiate PerformRemainingTasks for MM and SMM. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Enable CodeAccessCheck in MM Entry PointJiaxin Wu2024-08-284-23/+50
| | | | | | | | | | | | | | | | | | | | | | | For MM: CodeAccessCheck is designed to enable in the MM CPU Driver Entry Point. For SMM: CodeAccessCheck is still enabled in the first SMI when SMM ready to lock happen. This patch enables the CodeAccessCheck in MM CPU Driver Entry Point for MM support. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refactor code to create default Page TableJiaxin Wu2024-08-287-74/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For MM: Since all accessible NON-MMRAM memory and attribute shall be in ResourceDescriptor HOBs for MM, the page table for MM can be finalized and created in the default Page. For SMM: There are still 2 steps for the finalized default Page: 1. Create default Page 2. update the page table in the first SMI when SMM ready to lock happen This patch to refactor the GenSmmPageTable() function to create the default Page Table for Both SMM and MM: 1. Create NonMmram MemoryRegion 2. Gen NonMmram MemoryRegion PageTable 3. Gen MMRAM Range PageTable 4. Consider PcdCpuSmmStackGuard & PcdNullPointerDetectionPropertyMask cases. Meanwhile, mXdSupported needs to be initialized before GenSmmPageTable since it's required by GenSmmPageTable function. So, move the mXdSupported init from CheckFeatureSupported to the common EntryPoint function. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add PiCpuStandaloneMmEntry for MMJiaxin Wu2024-08-281-0/+46
| | | | | | | | | | | | | | | | | | | | | This patch adds the PiCpuStandaloneMmEntry for MM, which is the module Entry Point of the CPU StandaloneMm driver. In the Entry Point: 1. Init the mIsStandaloneMm flag 2. Call PiSmmCpuEntryCommon 3. Init SmiCommandPort 4. Install the SMM Configuration Protocol. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add GetSupportedMaxLogicalProcessorNumberJiaxin Wu2024-08-284-11/+54
| | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuMaxLogicalProcessorNumber), so move the PCD usage to DxeSmm. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl IsSmmCommBufferForbiddenAddress for MMJiaxin Wu2024-08-281-0/+28
| | | | | | | | | | | | | | | | Since all accessible NON-MMRAM memory shall be in ResourceDescriptor HOBs, check the ResourceDescriptor HOBs to return if the Address is forbidden or not for MM CPU. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Define mIsStandaloneMm to indicate SMM or MMJiaxin Wu2024-08-284-3/+41
| | | | | | | | | | | | | | | | | | | | Define the mIsStandaloneMm to indicate it's the MM_STANDALONE MM CPU driver or DXE_SMM_DRIVER SMM CPU driver execution. With mIsStandaloneMm, GetMpInformationFromMpServices() can be skipped for the MM CPU since it can not call the GetMpInformationFromMpServices() due to the NON-SMM MP Services usage for the MP Information. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmiCommandPort for MMJiaxin Wu2024-08-281-0/+13
| | | | | | | | | | | | | | | | MM CPU can not call EfiLocateFirstAcpiTable to get the system port address of the SMI Command Port. This patch just hard-code to 0xB2 for MM CPU. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl CreateExtendedProtectionRange for MMJiaxin Wu2024-08-282-2/+86
| | | | | | | | | | | | | | | | | According Standalone MM design, all accessible NON-MMRAM memory shall be in ResourceDescriptor HOBs. So, This patch consumes the Resource HOBs to create extended protection MemoryRegion and add them into protected memory ranges. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmmCpuSyncConfigData for MMJiaxin Wu2024-08-282-0/+46
| | | | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuSmmSyncMode & PcdCpuSmmApSyncTimeout & PcdCpuSmmApSyncTimeout2), so, it consumes the gMmCpuSyncConfigHobGuid for RelaxedApMode & Timeout & Timeout2. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetAcpiS3EnableFlag for MMJiaxin Wu2024-08-282-0/+29
| | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdAcpiS3Enable), so, it consumes the gMmAcpiS3EnableHobGuid to get ACPI S3 enable flag. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Impl GetSmmProfileData for MMJiaxin Wu2024-08-282-0/+40
| | | | | | | | | | | | | | | | MM CPU can not use the dynamic PCD (PcdCpuSmmProfileSize), so it consumes the gMmProfileDataHobGuid memory allocation hob for SmmProfile base address & size. Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add empty .c for MM CPU specific implJiaxin Wu2024-08-282-0/+18
| | | | | | | | | | | | | | | | This patch adds the empty .c for MM CPU specific implementation： NonMmramMapStandaloneMm.c PiSmmCpuStandaloneMm.c Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Dun Tan <dun.tan@intel.com> Cc: Hongbin1 Zhang <hongbin1.zhang@intel.com> Cc: Wei6 Xu <wei6.xu@intel.com> Cc: Yuanhao Xie <yuanhao.xie@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 10:50:05 +0000