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* UefiCpuPkg/PiSmmCpuDxeSmm: Fix bitwise size issueJian J Wang2017-10-161-1/+1
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/S3Resume2Pei: Handle Communicate Ppi not exist issue.Eric Dong2017-10-131-13/+10
| | | | | | | | | | | | | | Current code assume Communicate Ppi always existed, so it adds ASSERT to confirm it. Ovmf platform happened not has this Ppi, so the ASSERT been trig. This patch handle Ppi not existed case. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/S3Resume2Pei: Send S3 resume finished event to SmmCore.Eric Dong2017-10-122-0/+91
| | | | | | | | | | | | | | | | | | | | | Driver will send S3 resume finished event to SmmCore through communicate buffer after it signals EndOfPei event. V2 Changes: 1. Change structures name to avoid they start with EFI_. 2. Base on DXE phase bits to provide communication buffer, current implement check both PEI and DXE phase. V3 Changes: 1. Change structure name for better understanding. 2. Enhance communication buffer calculate logic to more accurate. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Implement NULL pointer detection for SMM codeJian J Wang2017-10-114-1/+49
| | | | | | | | | | | | | | | | | The mechanism behind is the same as NULL pointer detection enabled in EDK-II core. SMM has its own page table and we have to disable page 0 again in SMM mode. Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ayellet Wolman <ayellet.wolman@intel.com> Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Update Guid usage in DxeMpInitLib INF to match source code logicLiming Gao2017-10-101-1/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add check to void use null pointer.Eric Dong2017-10-091-0/+2
| | | | | | | | | | | Current code logic not check the pointer before use it. This may has potential issue, this patch add code to check it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Fix assert issue on IA32 platformJian J Wang2017-09-301-10/+40
| | | | | | | | | | | | | | | | | This patch is to fix an assert issue during booting IA32 platforms such as OvmfIa32 or Quark. This issue is caused by trying to access page table on a platform without page table. A check is added to avoid the assert. Bug tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=724 Cc: Star Zeng <star.zeng@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine codeChris Ruffin2017-09-294-29/+34
| | | | | | | | | | | | Replace hard-coded machine code with equivalent assembly source code. Changes tested by checking for machine code equivalence by disassembling the original and changed code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin <chris.ruffin@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code.Eric Dong2017-09-291-60/+24
| | | | | | | | | | | | | | | V2: Change function parameter to avoid touch global info in function. Enhance function name, make it more user friendly V1: Refine code to avoid duplicate code to set processor register. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI.Eric Dong2017-09-291-25/+26
| | | | | | | | | | | | In S3 resume path, current implementation do 2 separate INIT-SIPI-SIPI, this is not necessary. This change combine these 2 INIT-SIPI-SIPI to 1 and add CpuPause between them. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Add check for input parameter.Eric Dong2017-09-272-0/+4
| | | | | | | | | | | The ConfigData parameter initialized in *GetConfigData function should not be NULL in later *Support, *Initilize function, so just add ASSERT code check in these functions. Cc: Ming Shao <ming.shao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuDxe: Add missing function description commentsDandan Bi2017-09-271-0/+3
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Jian J Wang <jian.j.wang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* UefiCpuPkg/CpuDxe: Fix GCC build warningJian J Wang2017-09-221-2/+6
| | | | | | | | | | | | | There're uninitialized variables warning reported by GCC. This patch will fix it. The original commit is c1cab54ce57c2608b8b3ea051c7041f036f21153 Cc: Hao Wu <hao.a.wu@intel.com> Cc: Anthony PERARD <anthony.perard@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* UefiCpuPkg/CpuDxe: Fix out-of-sync issue in page attributesJian J Wang2017-09-213-0/+113
| | | | | | | | | | | | | | | | From CpuDxe driver perspective, it doesn't update GCD memory attributes from current page table setup during its initialization. So the memory attributes in GCD might not reflect all memory attributes in real world. Cc: Eric Dong <eric.dong@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Suggested-by: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/CpuDxe: log informative message at DEBUG_INFO levelLaszlo Ersek2017-09-111-1/+1
| | | | | | | | | | "Detect CPU count: %d\n" is an informative message, not an error report. Set its debug mask to DEBUG_INFO. Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Lmce.c Remove useless file.Eric Dong2017-09-051-97/+0
| | | | | | | | | Merge the code to MachineCheck.c file, remove this file. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: ApicLibLeo Duran2017-09-052-94/+30
| | | | | | | | | | | | | GetProcessorLocationByApicId () - Use max possible thread count to decode InitialApicId on AMD processor. - Clean-up on C Coding standards. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/Mplib.c: Perform complete initialization when enable AP.Eric Dong2017-08-311-1/+1
| | | | | | | | | | | | | | PI has description said If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system. Current implementation just set the AP to idle state when enable this AP which is not follow spec. This patch fix it. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Remove unnecessary explicit type castHao Wu2017-08-301-1/+1
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definitionStar Zeng2017-08-283-3/+2
| | | | | | | | | | | | | | | | | | | | Originally (before 714c2603018a99a514c42c2b511c821f30ba9cdf), mPhysicalAddressBits was only defined in X64 PageTbl.c, after 714c2603018a99a514c42c2b511c821f30ba9cdf, mPhysicalAddressBits is also defined in Ia32 PageTbl.c, then mPhysicalAddressBits is used in ConvertMemoryPageAttributes() for address check. This patch is to centralize mPhysicalAddressBits definition to PiSmmCpuDxeSmm.c from Ia32 and X64 PageTbl.c. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Suggested-by: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file.Eric Dong2017-08-282-1/+81
| | | | | | | | | | | | | Original code about Local Machine Check exception feature saves in a discrete file, because features related to machine check architecture all saved in MachineCheck.c file. This patch moved LMCE logic to same file for easy maintenance. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Add CPUID MCA support checkEric Dong2017-08-281-0/+4
| | | | | | | | | | | | Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Update default for ↵Eric Dong2017-08-282-17/+21
| | | | | | | | | | | | | | | PcdCpuProcTraceMemSize/PcdCpuProcTraceOutputScheme. These two definitions have redundant definition which can be handle by code. This patch update them to follow new code definitions. V2: Add more comments for the PCDs and keep consistent in .dec and .uni files. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Remove redundant definition.Eric Dong2017-08-281-9/+8
| | | | | | | | | | | | | | The EnumProcTraceMemDisable/OutputSchemeInvalid are redundant definitions. These definitions can be handled by other code, so remove them. V2: Change enum members name. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Use MSR data structure when change MSR value.Eric Dong2017-08-281-55/+61
| | | | | | | | | | | | | | When update MSR values, current code use BITxx to modify it. Enhance the code to use corresponding MSR's data structures to make it more user friendly. V2: Move architecturalMsr.h file. definition to architecturalMsr.h file. Use structure members to do value assignment. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.Eric Dong2017-08-281-1/+78
| | | | | | | | | | | | Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/MpLib: fix potential overflow issue.Eric Dong2017-08-281-10/+33
| | | | | | | | | | | | | | | Current calculate timeout logic may have overflow if the input timeout value too large. This patch fix this potential overflow issue. V2: Use local variable instead of call GetPerformanceCounterProperties twice. Also correct some comments. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory protection crashStar Zeng2017-08-283-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=624 reports memory protection crash in PiSmmCpuDxeSmm, Ia32 build with RAM above 4GB (of which 2GB are placed in 64-bit address). It is because UEFI builds identity mapping page tables, >4G address is not supported at Ia32 build. This patch is to get the PhysicalAddressBits that is used to build in PageTbl.c(Ia32/X64), and use it to check whether the address is supported or not in ConvertMemoryPageAttributes(). With this patch, the debug messages will be like below. UefiMemory protection: 0x0 - 0x9F000 Success UefiMemory protection: 0x100000 - 0x807000 Success UefiMemory protection: 0x808000 - 0x810000 Success UefiMemory protection: 0x818000 - 0x820000 Success UefiMemory protection: 0x1510000 - 0x7B798000 Success UefiMemory protection: 0x7B79B000 - 0x7E538000 Success UefiMemory protection: 0x7E539000 - 0x7E545000 Success UefiMemory protection: 0x7E55A000 - 0x7E61F000 Success UefiMemory protection: 0x7E62B000 - 0x7F6AB000 Success UefiMemory protection: 0x7F703000 - 0x7F70B000 Success UefiMemory protection: 0x7F70F000 - 0x7F778000 Success UefiMemory protection: 0x100000000 - 0x180000000 Unsupported Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Originally-suggested-by: Jiewen Yao <jiewen.yao@intel.com> Reported-by: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/PiSmmCpuDxeSmm: Add CPUID MCA support checkMichael D Kinney2017-08-171-2/+14
| | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=674 Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs. Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Fix buffer pointer error usage.Eric Dong2017-08-171-8/+8
| | | | | | | | | | | | | | | | | Current code allocate buffer for the pointer which later get value from PCD database. but current code error use "=" for this case. Use AllocateCopyPool instead to fix it. V2 enhanced to directly use AllocateCopyPool to get the PCD value. V3 enhanced to avoid using local temp variable. V4 enhanced to keep the functions to get the pcd values. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Shao Ming <ming.shao@intel.com> Cc: Kinney Michael D <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
* UefiCpuPkg/BaseUefiCpuLib.inf: Remove unnecessary library class.Eric Dong2017-08-161-5/+1
| | | | | | | | | | | UefiCpuLib inf file reference itself in [LibraryClasses] section, this is not necessary. This patch remove it. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Ming Shao <ming.shao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Enhance debug messages.Eric Dong2017-08-161-4/+4
| | | | | | | | | | | Current debug message when enable/disable CPU feature not correct. This patch enhances it to make it more accurate. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Shao, Ming <ming.shao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg UefiCpupkg.uni: Add new pcds comments.Eric Dong2017-08-161-0/+30
| | | | | | | | | | | Add prompt/help string for pcd PcdCpuProcTraceOutputScheme and PcdCpuProcTraceMemSize in UefiCpuPkg.uni file. Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg: Add comments for PCDs definition.Eric Dong2017-08-161-2/+26
| | | | | | | | | | | | Add valid/default values for PCD PcdCpuProcTraceMemSize and PcdCpuProcTraceOutputScheme in the comment part. Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg MpInitLib: Save/restore original WakeupBuffer for DxeMpLibStar Zeng2017-08-154-168/+109
| | | | | | | | | | | | | | | | | | | | | Current code always allocates/frees < 1MB WakeupBuffer for DxeMpLib until ExitBootService, but the allocation may be failed at late phase of the boot. This patch is to always save/restore original WakeupBuffer for DxeMpLib, it is aligned with the solution for PeiMpLib at 9293d6e42e677e4a38e055258c0993ad8a9df14e, then AllocateResetVector() and FreeResetVector() will be common and moved to MpLib.c. Only difference is GetWakeupBuffer() that will be in PeiMpLib or DxeMpLib respectively. Cc: Liming Gao <liming.gao@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg MtrrLib: Remove deprecated micro.Eric Dong2017-08-071-27/+0
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Remove reference deprecated macro.Eric Dong2017-08-072-11/+12
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg CpuDxe: Enhance get mtrr mask logic.Eric Dong2017-08-071-7/+6
| | | | | | | | | | | In order to not use the deprecated macro, refine get mtrr mask value logic. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Enable Processor Trace feature.Eric Dong2017-08-044-1/+543
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add Processor Trace feature definition.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add Pcds used by processor trace feature.Eric Dong2017-08-041-0/+8
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/Msr: Add a missing IvyBridge processor signatureHao Wu2017-08-041-1/+2
| | | | | | | | | | | This commit modifies the CPUID signature check MACRO for IvyBridge processor by adding a missing DisplayModel 0x3E. The missing one appears at Section 35.10.1 to Section 35.10.3 of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg PiSmmCpuDxeSmm: Check LMCE capability when wait for AP.Eric Dong2017-08-041-1/+56
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature.Eric Dong2017-08-044-0/+158
| | | | | | | Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg: Add definition for LMCE feature.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* edk2: Move License.txt file to rootMichael D Kinney2017-08-031-25/+0
| | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=642 Add top level License.txt file with the BSD 2-Clause License that is used by the majority of the EKD II open source project content. Merge copyright statements from the BSD 2-Clause License files in each package directory and remove the duplication License.txt file from package directories. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* edk2: Move TianoCore Contribution Agreement to rootMichael D Kinney2017-08-031-218/+0
| | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=629 Move Contributions.txt that contains the TianoCore Contribution Agreement 1.0 to the root of the edk2 repository and remove the duplicate Contributions.txt files from all packages. Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Andrew Fish <afish@apple.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* UefiCpuPkg/CpuCommonFeaturesLib: Fix the documentation of PpinSupport().Marvin.Haeuser@outlook.com2017-08-032-4/+4
| | | | | | | | | The documentation of PpinSupport() refers to 'Enhanced Intel SpeedStep'. This patch fixes these referneces. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg SecCore: Fix operands of different size in bitwise operationStar Zeng2017-08-021-1/+1
| | | | | | | | | | | | It is introduced by 9e9ca2100f22be29f1a53129d741f4305ff34a71. Cc: Hao Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg SecCore: Add SecPerformancePpiCallBackStar Zeng2017-08-013-1/+77
| | | | | | | | | | | | Add SecPerformancePpiCallBack to get SEC performance data and build HOB to convey the SEC performance data to DXE phase. Cc: Liming Gao <liming.gao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 06:44:24 +0000