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/** @file
FACP Table
Copyright (c) 2013, Red Hat, Inc.
Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "Platform.h"
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
{
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
0, // to make sum of entire table == 0
{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
EFI_ACPI_OEM_REVISION, // OEM revision number
EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
},
0, // Physical address of FACS
0, // Physical address of DSDT
RESERVED, // System Interrupt Model in ACPI 1.0, eliminated in 2.0
EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED, // Preferred PM profile
SCI_INT_VECTOR, // System vector of SCI interrupt
SMI_CMD_IO_PORT, // Port address of SMI command port
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
0, // PState control
PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
0, // Power Mgt 1b Event Reg Blk unsupported
PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
0, // Power Mgt 1b Ctrl Reg Blk unsupported
0, // Power Mgt 2 Ctrl Reg Blk unsupported
PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk
GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk
0, // General Purpose Event 1 Reg Blk unsupported
PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
0, // Power Mgt 2 Ctrl Reg Blk unsupported
PM_TM_LEN, // Byte Length of ports at pm_tm_blk
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
0, // General Purpose Event 1 Reg Blk unsupported
0, // General Purpose Event 1 Reg Blk unsupported
0, // _CST support
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
FLUSH_SIZE, // Size of area read to flush caches
FLUSH_STRIDE, // Stride used in flushing caches
DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
CENTURY, // index to century in RTC CMOS RAM
0x0000, // Boot architecture flag (16-bit)
RESERVED, // reserved
FLAG, // Fixed feature flags
GAS2_IO(RESET_REG, 1), // Extended address of the Reset Register
RESET_VALUE, // Value for the Reset Register to reset the system
{ RESERVED }, // reserved[3]
0, // 64-bit physical address of FACS, set at installation
0, // 64-bit physical address of DSDT, set at installation
GAS2_IO(PM1a_EVT_BLK, PM1_EVT_LEN), // Ext. addr. of PM 1a Event Reg Blk
{ 0 }, // PM 1b Event Reg Blk unsupported
GAS2_IO(PM1a_CNT_BLK, PM1_CNT_LEN), // Ext. addr. of PM 1a Ctrl Reg Blk
{ 0 }, // PM 1b Ctrl Reg Blk unsupported
{ 0 }, // PM 2 Ctrl Reg Blk unsupported
GAS2_IO(PM_TMR_BLK, PM_TM_LEN), // Ext. addr. of PM Timer Ctrl Reg Blk
GAS2_IO(GPE0_BLK, GPE0_BLK_LEN), // Ext. addr. of GPE 0 Reg Blk
{ 0 } // GPE 1 Reg Blk unsupported
};
VOID*
ReferenceAcpiTable (
VOID
)
{
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
return (VOID*)&FACP;
}
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