blob: 24e4da4e1d93ebb481546165e39ebc0cacb952a4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
/** @file
Platform PEI module include file.
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PLATFORM_PEI_H_INCLUDED_
#define _PLATFORM_PEI_H_INCLUDED_
#include <IndustryStandard/E820.h>
VOID
AddIoMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
);
VOID
AddIoMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize
);
VOID
AddMemoryRangeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
EFI_PHYSICAL_ADDRESS MemoryLimit
);
VOID
AddReservedMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
UINT64 MemorySize,
BOOLEAN Cacheable
);
VOID
AddressWidthInitialization (
VOID
);
VOID
Q35TsegMbytesInitialization (
VOID
);
VOID
Q35SmramAtDefaultSmbaseInitialization (
VOID
);
EFI_STATUS
PublishPeiMemory (
VOID
);
UINT32
GetSystemMemorySizeBelow4gb (
VOID
);
VOID
QemuUc32BaseInitialization (
VOID
);
VOID
InitializeRamRegions (
VOID
);
EFI_STATUS
PeiFvInitialization (
VOID
);
VOID
MemTypeInfoInitialization (
VOID
);
VOID
InstallFeatureControlCallback (
VOID
);
VOID
InstallClearCacheCallback (
VOID
);
VOID
AmdSevInitialize (
VOID
);
extern EFI_BOOT_MODE mBootMode;
VOID
SevInitializeRam (
VOID
);
extern BOOLEAN mS3Supported;
extern UINT8 mPhysMemAddressWidth;
extern UINT32 mMaxCpuCount;
extern UINT16 mHostBridgeDevId;
extern BOOLEAN mQ35SmramAtDefaultSmbase;
extern UINT32 mQemuUc32Base;
#endif // _PLATFORM_PEI_H_INCLUDED_
|
