1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
|
/** @file
Header file for the SPI flash module.
Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef SPI_COMMON_LIB_H_
#define SPI_COMMON_LIB_H_
#include <PiDxe.h>
#include <Uefi/UefiBaseType.h>
#include <IndustryStandard/Pci30.h>
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/SpiFlashLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/HobLib.h>
#include <Library/TimerLib.h>
#include <Guid/SpiFlashInfoGuid.h>
#include "RegsSpi.h"
///
/// Maximum time allowed while waiting the SPI cycle to complete
/// Wait Time = 6 seconds = 6000000 microseconds
/// Wait Period = 10 microseconds
///
#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
///
/// Flash cycle Type
///
typedef enum {
FlashCycleRead,
FlashCycleWrite,
FlashCycleErase,
FlashCycleReadSfdp,
FlashCycleReadJedecId,
FlashCycleWriteStatus,
FlashCycleReadStatus,
FlashCycleMax
} FLASH_CYCLE_TYPE;
///
/// Flash Component Number
///
typedef enum {
FlashComponent0,
FlashComponent1,
FlashComponentMax
} FLASH_COMPONENT_NUM;
///
/// Private data structure definitions for the driver
///
#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
typedef struct {
UINTN Signature;
EFI_HANDLE Handle;
UINT32 AcpiTmrReg;
UINTN PchSpiBase;
UINT16 RegionPermission;
UINT32 SfdpVscc0Value;
UINT32 SfdpVscc1Value;
UINT32 StrapBaseAddress;
UINT8 NumberOfComponents;
UINT16 Flags;
UINT32 Component1StartAddr;
} SPI_INSTANCE;
/**
Acquire SPI MMIO BAR
@param[in] PchSpiBase PCH SPI PCI Base Address
@retval Return SPI BAR Address
**/
UINT32
AcquireSpiBar0 (
IN UINTN PchSpiBase
);
/**
Release SPI MMIO BAR. Do nothing.
@param[in] PchSpiBase PCH SPI PCI Base Address
@retval None
**/
VOID
ReleaseSpiBar0 (
IN UINTN PchSpiBase
);
/**
This function is a hook for Spi to disable BIOS Write Protect
@param[in] PchSpiBase PCH SPI PCI Base Address
@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
@retval EFI_SUCCESS The protocol instance was properly initialized
@retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
**/
EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
);
/**
This function is a hook for Spi to enable BIOS Write Protect
@param[in] PchSpiBase PCH SPI PCI Base Address
@param[in] CpuSmmBwp Need to disable CPU SMM Bios write protection or not
@retval None
**/
VOID
EFIAPI
EnableBiosWriteProtect (
IN UINTN PchSpiBase,
IN UINT8 CpuSmmBwp
);
/**
This function disables SPI Prefetching and caching,
and returns previous BIOS Control Register value before disabling.
@param[in] PchSpiBase PCH SPI PCI Base Address
@retval Previous BIOS Control Register value
**/
UINT8
SaveAndDisableSpiPrefetchCache (
IN UINTN PchSpiBase
);
/**
This function updates BIOS Control Register with the given value.
@param[in] PchSpiBase PCH SPI PCI Base Address
@param[in] BiosCtlValue BIOS Control Register Value to be updated
@retval None
**/
VOID
SetSpiBiosControlRegister (
IN UINTN PchSpiBase,
IN UINT8 BiosCtlValue
);
/**
This function sends the programmed SPI command to the slave device.
@param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
@param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
@param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
@param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
@param[in,out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle.
@retval EFI_SUCCESS SPI command completes successfully.
@retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
@retval EFI_ACCESS_DENIED Some unrecognized command encountered in hardware sequencing mode
@retval EFI_INVALID_PARAMETER The parameters specified are not valid.
**/
EFI_STATUS
SendSpiCmd (
IN FLASH_REGION_TYPE FlashRegionType,
IN FLASH_CYCLE_TYPE FlashCycleType,
IN UINT32 Address,
IN UINT32 ByteCount,
IN OUT UINT8 *Buffer
);
/**
Wait execution cycle to complete on the SPI interface.
@param[in] PchSpiBar0 Spi MMIO base address
@param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
@retval TRUE SPI cycle completed on the interface.
@retval FALSE Time out while waiting the SPI cycle to complete.
It's not safe to program the next command on the SPI interface.
**/
BOOLEAN
WaitForSpiCycleComplete (
IN UINT32 PchSpiBar0,
IN BOOLEAN ErrorCheck
);
#endif
|
