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authorSean Nelson <audiohacked@gmail.com>2010-02-26 05:48:29 +0000
committerSean Nelson <audiohacked@gmail.com>2010-02-26 05:48:29 +0000
commit14ba6682e99273273be74b8e8681d0604b85e9b9 (patch)
treecd0212ae1ffe83aaea0a5ca9f5e2be86615c471a
parentcfa674fde7ee763844f82e38503cd997a3951197 (diff)
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Split spi.c into programmer and chip code Remove chipdriver.h include from flash.h
Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c Corresponding to flashrom svn r914. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
-rw-r--r--82802ab.c1
-rw-r--r--Makefile2
-rw-r--r--bitbang_spi.c1
-rw-r--r--buspirate_spi.c1
-rw-r--r--dediprog.c1
-rw-r--r--flash.h2
-rw-r--r--flashchips.c1
-rw-r--r--ft2232_spi.c1
-rw-r--r--ichspi.c1
-rw-r--r--it87spi.c1
-rw-r--r--jedec.c1
-rw-r--r--m29f400bt.c1
-rw-r--r--pm49fl00x.c1
-rw-r--r--sb600spi.c1
-rw-r--r--sharplhf00l04.c1
-rw-r--r--spi.c936
-rw-r--r--spi25.c992
-rw-r--r--sst28sf040.c1
-rw-r--r--sst49lfxxxc.c1
-rw-r--r--sst_fwhub.c1
-rw-r--r--stm50flw0x0x.c1
-rw-r--r--w29ee011.c1
-rw-r--r--w39v040c.c1
-rw-r--r--w39v080fa.c1
-rw-r--r--wbsio_spi.c1
25 files changed, 1015 insertions, 938 deletions
diff --git a/82802ab.c b/82802ab.c
index dfe81e833..e63dc1007 100644
--- a/82802ab.c
+++ b/82802ab.c
@@ -29,6 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include "flash.h"
+#include "chipdrivers.h"
// I need that Berkeley bit-map printer
void print_82802ab_status(uint8_t status)
diff --git a/Makefile b/Makefile
index d5132a7a9..924562479 100644
--- a/Makefile
+++ b/Makefile
@@ -43,7 +43,7 @@ endif
CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o sharplhf00l04.o w29ee011.o \
sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \
- sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o
+ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o
LIB_OBJS = layout.o
diff --git a/bitbang_spi.c b/bitbang_spi.c
index 892588477..8d6a9a1f7 100644
--- a/bitbang_spi.c
+++ b/bitbang_spi.c
@@ -23,6 +23,7 @@
#include <stdlib.h>
#include <ctype.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
/* Length of half a clock period in usecs */
diff --git a/buspirate_spi.c b/buspirate_spi.c
index ecdd68986..f1a0be1d6 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -23,6 +23,7 @@
#include <stdlib.h>
#include <ctype.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
/* Change this to #define if you want to test without a serial implementation */
diff --git a/dediprog.c b/dediprog.c
index c6d2a30f2..2d0d060c0 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -23,6 +23,7 @@
#include <sys/types.h>
#include <usb.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
#define DEFAULT_TIMEOUT 3000
diff --git a/flash.h b/flash.h
index ff2004c90..76be16485 100644
--- a/flash.h
+++ b/flash.h
@@ -681,6 +681,4 @@ int serialport_shutdown(void);
int serialport_write(unsigned char *buf, unsigned int writecnt);
int serialport_read(unsigned char *buf, unsigned int readcnt);
-#include "chipdrivers.h"
-
#endif /* !__FLASH_H__ */
diff --git a/flashchips.c b/flashchips.c
index 875d5b3a6..45e67c64e 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -24,6 +24,7 @@
#include "flash.h"
#include "flashchips.h"
+#include "chipdrivers.h"
/**
* List of supported flash chips.
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 6e029c2b7..97b4867fb 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -26,6 +26,7 @@
#include <stdlib.h>
#include <ctype.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
#include <ftdi.h>
diff --git a/ichspi.c b/ichspi.c
index 77d236a5c..9ab61ffb0 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -35,6 +35,7 @@
#include <string.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
/* Change this to #define if you want lowlevel debugging of commands
diff --git a/it87spi.c b/it87spi.c
index fcbf086a7..ed72c9006 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -26,6 +26,7 @@
#include <string.h>
#include <stdlib.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
#define ITE_SUPERIO_PORT1 0x2e
diff --git a/jedec.c b/jedec.c
index 055e91029..fee73028d 100644
--- a/jedec.c
+++ b/jedec.c
@@ -23,6 +23,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
#define MAX_REFLASH_TRIES 0x10
#define MASK_FULL 0xffff
diff --git a/m29f400bt.c b/m29f400bt.c
index e77572aed..c39407459 100644
--- a/m29f400bt.c
+++ b/m29f400bt.c
@@ -19,6 +19,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
/* WARNING!
This chip uses the standard JEDEC Addresses in 16-bit mode as word
diff --git a/pm49fl00x.c b/pm49fl00x.c
index e8c498d03..17a49f0a9 100644
--- a/pm49fl00x.c
+++ b/pm49fl00x.c
@@ -21,6 +21,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
void write_lockbits_49fl00x(chipaddr bios, int size,
unsigned char bits, int block_size)
diff --git a/sb600spi.c b/sb600spi.c
index 9172eacee..0cf797c3f 100644
--- a/sb600spi.c
+++ b/sb600spi.c
@@ -22,6 +22,7 @@
#include <string.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
/* This struct is unused, but helps visualize the SB600 SPI BAR layout.
diff --git a/sharplhf00l04.c b/sharplhf00l04.c
index 9669e2021..d5ab38cb2 100644
--- a/sharplhf00l04.c
+++ b/sharplhf00l04.c
@@ -20,6 +20,7 @@
#include <stdlib.h>
#include "flash.h"
+#include "chipdrivers.h"
// I need that Berkeley bit-map printer
void print_lhf00l04_status(uint8_t status)
diff --git a/spi.c b/spi.c
index 66f1db875..41bb8f31e 100644
--- a/spi.c
+++ b/spi.c
@@ -25,6 +25,7 @@
#include <string.h>
#include "flash.h"
#include "flashchips.h"
+#include "chipdrivers.h"
#include "spi.h"
enum spi_controller spi_controller = SPI_CONTROLLER_NONE;
@@ -178,873 +179,6 @@ int default_spi_send_multicommand(struct spi_command *cmds)
return result;
}
-static int spi_rdid(unsigned char *readarr, int bytes)
-{
- const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
- int ret;
- int i;
-
- ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
- if (ret)
- return ret;
- printf_debug("RDID returned");
- for (i = 0; i < bytes; i++)
- printf_debug(" 0x%02x", readarr[i]);
- printf_debug(". ");
- return 0;
-}
-
-static int spi_rems(unsigned char *readarr)
-{
- unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
- uint32_t readaddr;
- int ret;
-
- ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
- if (ret == SPI_INVALID_ADDRESS) {
- /* Find the lowest even address allowed for reads. */
- readaddr = (spi_get_valid_read_addr() + 1) & ~1;
- cmd[1] = (readaddr >> 16) & 0xff,
- cmd[2] = (readaddr >> 8) & 0xff,
- cmd[3] = (readaddr >> 0) & 0xff,
- ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
- }
- if (ret)
- return ret;
- printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
- return 0;
-}
-
-static int spi_res(unsigned char *readarr)
-{
- unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
- uint32_t readaddr;
- int ret;
-
- ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
- if (ret == SPI_INVALID_ADDRESS) {
- /* Find the lowest even address allowed for reads. */
- readaddr = (spi_get_valid_read_addr() + 1) & ~1;
- cmd[1] = (readaddr >> 16) & 0xff,
- cmd[2] = (readaddr >> 8) & 0xff,
- cmd[3] = (readaddr >> 0) & 0xff,
- ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
- }
- if (ret)
- return ret;
- printf_debug("RES returned %02x. ", readarr[0]);
- return 0;
-}
-
-int spi_write_enable(void)
-{
- const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
- int result;
-
- /* Send WREN (Write Enable) */
- result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
-
- if (result)
- fprintf(stderr, "%s failed\n", __func__);
-
- return result;
-}
-
-int spi_write_disable(void)
-{
- const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
-
- /* Send WRDI (Write Disable) */
- return spi_send_command(sizeof(cmd), 0, cmd, NULL);
-}
-
-static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
-{
- unsigned char readarr[4];
- uint32_t id1;
- uint32_t id2;
-
- if (spi_rdid(readarr, bytes))
- return 0;
-
- if (!oddparity(readarr[0]))
- printf_debug("RDID byte 0 parity violation. ");
-
- /* Check if this is a continuation vendor ID */
- if (readarr[0] == 0x7f) {
- if (!oddparity(readarr[1]))
- printf_debug("RDID byte 1 parity violation. ");
- id1 = (readarr[0] << 8) | readarr[1];
- id2 = readarr[2];
- if (bytes > 3) {
- id2 <<= 8;
- id2 |= readarr[3];
- }
- } else {
- id1 = readarr[0];
- id2 = (readarr[1] << 8) | readarr[2];
- }
-
- printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
-
- if (id1 == flash->manufacture_id && id2 == flash->model_id) {
- /* Print the status register to tell the
- * user about possible write protection.
- */
- spi_prettyprint_status_register(flash);
-
- return 1;
- }
-
- /* Test if this is a pure vendor match. */
- if (id1 == flash->manufacture_id &&
- GENERIC_DEVICE_ID == flash->model_id)
- return 1;
-
- /* Test if there is any vendor ID. */
- if (GENERIC_MANUF_ID == flash->manufacture_id &&
- id1 != 0xff)
- return 1;
-
- return 0;
-}
-
-int probe_spi_rdid(struct flashchip *flash)
-{
- return probe_spi_rdid_generic(flash, 3);
-}
-
-/* support 4 bytes flash ID */
-int probe_spi_rdid4(struct flashchip *flash)
-{
- /* only some SPI chipsets support 4 bytes commands */
- switch (spi_controller) {
-#if INTERNAL_SUPPORT == 1
- case SPI_CONTROLLER_ICH7:
- case SPI_CONTROLLER_ICH9:
- case SPI_CONTROLLER_VIA:
- case SPI_CONTROLLER_SB600:
- case SPI_CONTROLLER_WBSIO:
-#endif
-#if FT2232_SPI_SUPPORT == 1
- case SPI_CONTROLLER_FT2232:
-#endif
-#if DUMMY_SUPPORT == 1
- case SPI_CONTROLLER_DUMMY:
-#endif
-#if BUSPIRATE_SPI_SUPPORT == 1
- case SPI_CONTROLLER_BUSPIRATE:
-#endif
-#if DEDIPROG_SUPPORT == 1
- case SPI_CONTROLLER_DEDIPROG:
-#endif
- return probe_spi_rdid_generic(flash, 4);
- default:
- printf_debug("4b ID not supported on this SPI controller\n");
- }
-
- return 0;
-}
-
-int probe_spi_rems(struct flashchip *flash)
-{
- unsigned char readarr[JEDEC_REMS_INSIZE];
- uint32_t id1, id2;
-
- if (spi_rems(readarr))
- return 0;
-
- id1 = readarr[0];
- id2 = readarr[1];
-
- printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
-
- if (id1 == flash->manufacture_id && id2 == flash->model_id) {
- /* Print the status register to tell the
- * user about possible write protection.
- */
- spi_prettyprint_status_register(flash);
-
- return 1;
- }
-
- /* Test if this is a pure vendor match. */
- if (id1 == flash->manufacture_id &&
- GENERIC_DEVICE_ID == flash->model_id)
- return 1;
-
- /* Test if there is any vendor ID. */
- if (GENERIC_MANUF_ID == flash->manufacture_id &&
- id1 != 0xff)
- return 1;
-
- return 0;
-}
-
-int probe_spi_res(struct flashchip *flash)
-{
- unsigned char readarr[3];
- uint32_t id2;
- const unsigned char allff[] = {0xff, 0xff, 0xff};
- const unsigned char all00[] = {0x00, 0x00, 0x00};
-
- /* Check if RDID is usable and does not return 0xff 0xff 0xff or
- * 0x00 0x00 0x00. In that case, RES is pointless.
- */
- if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) &&
- memcmp(readarr, all00, 3)) {
- msg_cdbg("Ignoring RES in favour of RDID.\n");
- return 0;
- }
- /* Check if REMS is usable and does not return 0xff 0xff or
- * 0x00 0x00. In that case, RES is pointless.
- */
- if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
- memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
- msg_cdbg("Ignoring RES in favour of REMS.\n");
- return 0;
- }
-
- if (spi_res(readarr))
- return 0;
-
- /* FIXME: Handle the case where RES gives a 2-byte response. */
- id2 = readarr[0];
- printf_debug("%s: id 0x%x\n", __func__, id2);
- if (id2 != flash->model_id)
- return 0;
-
- /* Print the status register to tell the
- * user about possible write protection.
- */
- spi_prettyprint_status_register(flash);
- return 1;
-}
-
-uint8_t spi_read_status_register(void)
-{
- const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
- /* FIXME: No workarounds for driver/hardware bugs in generic code. */
- unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
- int ret;
-
- /* Read Status Register */
- ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
- if (ret)
- fprintf(stderr, "RDSR failed!\n");
-
- return readarr[0];
-}
-
-/* Prettyprint the status register. Common definitions. */
-void spi_prettyprint_status_register_common(uint8_t status)
-{
- printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
- "%sset\n", (status & (1 << 5)) ? "" : "not ");
- printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
- "%sset\n", (status & (1 << 4)) ? "" : "not ");
- printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
- "%sset\n", (status & (1 << 3)) ? "" : "not ");
- printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
- "%sset\n", (status & (1 << 2)) ? "" : "not ");
- printf_debug("Chip status register: Write Enable Latch (WEL) is "
- "%sset\n", (status & (1 << 1)) ? "" : "not ");
- printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
- "%sset\n", (status & (1 << 0)) ? "" : "not ");
-}
-
-/* Prettyprint the status register. Works for
- * ST M25P series
- * MX MX25L series
- */
-void spi_prettyprint_status_register_st_m25p(uint8_t status)
-{
- printf_debug("Chip status register: Status Register Write Disable "
- "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
- printf_debug("Chip status register: Bit 6 is "
- "%sset\n", (status & (1 << 6)) ? "" : "not ");
- spi_prettyprint_status_register_common(status);
-}
-
-void spi_prettyprint_status_register_sst25(uint8_t status)
-{
- printf_debug("Chip status register: Block Protect Write Disable "
- "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
- printf_debug("Chip status register: Auto Address Increment Programming "
- "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
- spi_prettyprint_status_register_common(status);
-}
-
-/* Prettyprint the status register. Works for
- * SST 25VF016
- */
-void spi_prettyprint_status_register_sst25vf016(uint8_t status)
-{
- const char *bpt[] = {
- "none",
- "1F0000H-1FFFFFH",
- "1E0000H-1FFFFFH",
- "1C0000H-1FFFFFH",
- "180000H-1FFFFFH",
- "100000H-1FFFFFH",
- "all", "all"
- };
- spi_prettyprint_status_register_sst25(status);
- printf_debug("Resulting block protection : %s\n",
- bpt[(status & 0x1c) >> 2]);
-}
-
-void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
-{
- const char *bpt[] = {
- "none",
- "0x70000-0x7ffff",
- "0x60000-0x7ffff",
- "0x40000-0x7ffff",
- "all blocks", "all blocks", "all blocks", "all blocks"
- };
- spi_prettyprint_status_register_sst25(status);
- printf_debug("Resulting block protection : %s\n",
- bpt[(status & 0x1c) >> 2]);
-}
-
-void spi_prettyprint_status_register(struct flashchip *flash)
-{
- uint8_t status;
-
- status = spi_read_status_register();
- printf_debug("Chip status register is %02x\n", status);
- switch (flash->manufacture_id) {
- case ST_ID:
- if (((flash->model_id & 0xff00) == 0x2000) ||
- ((flash->model_id & 0xff00) == 0x2500))
- spi_prettyprint_status_register_st_m25p(status);
- break;
- case MX_ID:
- if ((flash->model_id & 0xff00) == 0x2000)
- spi_prettyprint_status_register_st_m25p(status);
- break;
- case SST_ID:
- switch (flash->model_id) {
- case 0x2541:
- spi_prettyprint_status_register_sst25vf016(status);
- break;
- case 0x8d:
- case 0x258d:
- spi_prettyprint_status_register_sst25vf040b(status);
- break;
- default:
- spi_prettyprint_status_register_sst25(status);
- break;
- }
- break;
- }
-}
-
-int spi_chip_erase_60(struct flashchip *flash)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_CE_60_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_CE_60 },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_disable_blockprotect();
- if (result) {
- fprintf(stderr, "spi_disable_blockprotect failed\n");
- return result;
- }
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution\n",
- __func__);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 1-85 s, so wait in 1 s steps.
- */
- /* FIXME: We assume spi_read_status_register will never fail. */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(1000 * 1000);
- if (check_erased_range(flash, 0, flash->total_size * 1024)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-int spi_chip_erase_c7(struct flashchip *flash)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_CE_C7_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_disable_blockprotect();
- if (result) {
- fprintf(stderr, "spi_disable_blockprotect failed\n");
- return result;
- }
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution\n", __func__);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 1-85 s, so wait in 1 s steps.
- */
- /* FIXME: We assume spi_read_status_register will never fail. */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(1000 * 1000);
- if (check_erased_range(flash, 0, flash->total_size * 1024)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-int spi_chip_erase_60_c7(struct flashchip *flash)
-{
- int result;
- result = spi_chip_erase_60(flash);
- if (result) {
- printf_debug("spi_chip_erase_60 failed, trying c7\n");
- result = spi_chip_erase_c7(flash);
- }
- return result;
-}
-
-int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_BE_52_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_BE_52, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 100-4000 ms, so wait in 100 ms steps.
- */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(100 * 1000);
- if (check_erased_range(flash, addr, blocklen)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-/* Block size is usually
- * 64k for Macronix
- * 32k for SST
- * 4-32k non-uniform for EON
- */
-int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_BE_D8_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_BE_D8, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 100-4000 ms, so wait in 100 ms steps.
- */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(100 * 1000);
- if (check_erased_range(flash, addr, blocklen)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-/* Block size is usually
- * 4k for PMC
- */
-int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_BE_D7_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_BE_D7, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 100-4000 ms, so wait in 100 ms steps.
- */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(100 * 1000);
- if (check_erased_range(flash, addr, blocklen)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-int spi_chip_erase_d8(struct flashchip *flash)
-{
- int i, rc = 0;
- int total_size = flash->total_size * 1024;
- int erase_size = 64 * 1024;
-
- spi_disable_blockprotect();
-
- printf("Erasing chip: \n");
-
- for (i = 0; i < total_size / erase_size; i++) {
- rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
- if (rc) {
- fprintf(stderr, "Error erasing block at 0x%x\n", i);
- break;
- }
- }
-
- printf("\n");
-
- return rc;
-}
-
-/* Sector size is usually 4k, though Macronix eliteflash has 64k */
-int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_SE_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_SE, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff) },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- return result;
- }
- /* Wait until the Write-In-Progress bit is cleared.
- * This usually takes 15-800 ms, so wait in 10 ms steps.
- */
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(10 * 1000);
- if (check_erased_range(flash, addr, blocklen)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- return 0;
-}
-
-int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
- fprintf(stderr, "%s called with incorrect arguments\n",
- __func__);
- return -1;
- }
- return spi_chip_erase_60(flash);
-}
-
-int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
-{
- if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
- fprintf(stderr, "%s called with incorrect arguments\n",
- __func__);
- return -1;
- }
- return spi_chip_erase_c7(flash);
-}
-
-int spi_write_status_enable(void)
-{
- const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
- int result;
-
- /* Send EWSR (Enable Write Status Register). */
- result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
-
- if (result)
- fprintf(stderr, "%s failed\n", __func__);
-
- return result;
-}
-
-/*
- * This is according the SST25VF016 datasheet, who knows it is more
- * generic that this...
- */
-int spi_write_status_register(int status)
-{
- int result;
- struct spi_command cmds[] = {
- {
- /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
- .writecnt = JEDEC_EWSR_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_EWSR },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_WRSR_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution\n",
- __func__);
- }
- return result;
-}
-
-int spi_byte_program(int addr, uint8_t databyte)
-{
- int result;
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_BYTE_PROGRAM, (addr >> 16) & 0xff, (addr >> 8) & 0xff, (addr & 0xff), databyte },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- }
- return result;
-}
-
-int spi_nbyte_program(int addr, uint8_t *bytes, int len)
-{
- int result;
- /* FIXME: Switch to malloc based on len unless that kills speed. */
- unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
- JEDEC_BYTE_PROGRAM,
- (addr >> 16) & 0xff,
- (addr >> 8) & 0xff,
- (addr >> 0) & 0xff,
- };
- struct spi_command cmds[] = {
- {
- .writecnt = JEDEC_WREN_OUTSIZE,
- .writearr = (const unsigned char[]){ JEDEC_WREN },
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
- .writearr = cmd,
- .readcnt = 0,
- .readarr = NULL,
- }, {
- .writecnt = 0,
- .writearr = NULL,
- .readcnt = 0,
- .readarr = NULL,
- }};
-
- if (!len) {
- fprintf(stderr, "%s called for zero-length write\n", __func__);
- return 1;
- }
- if (len > 256) {
- fprintf(stderr, "%s called for too long a write\n", __func__);
- return 1;
- }
-
- memcpy(&cmd[4], bytes, len);
-
- result = spi_send_multicommand(cmds);
- if (result) {
- fprintf(stderr, "%s failed during command execution at address 0x%x\n",
- __func__, addr);
- }
- return result;
-}
-
-int spi_disable_blockprotect(void)
-{
- uint8_t status;
- int result;
-
- status = spi_read_status_register();
- /* If there is block protection in effect, unprotect it first. */
- if ((status & 0x3c) != 0) {
- printf_debug("Some block protection in effect, disabling\n");
- result = spi_write_status_register(status & ~0x3c);
- if (result) {
- fprintf(stderr, "spi_write_status_register failed\n");
- return result;
- }
- }
- return 0;
-}
-
-int spi_nbyte_read(int address, uint8_t *bytes, int len)
-{
- const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
- JEDEC_READ,
- (address >> 16) & 0xff,
- (address >> 8) & 0xff,
- (address >> 0) & 0xff,
- };
-
- /* Send Read */
- return spi_send_command(sizeof(cmd), len, cmd, bytes);
-}
-
-/*
- * Read a complete flash chip.
- * Each page is read separately in chunks with a maximum size of chunksize.
- */
-int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
-{
- int rc = 0;
- int i, j, starthere, lenhere;
- int page_size = flash->page_size;
- int toread;
-
- /* Warning: This loop has a very unusual condition and body.
- * The loop needs to go through each page with at least one affected
- * byte. The lowest page number is (start / page_size) since that
- * division rounds down. The highest page number we want is the page
- * where the last byte of the range lives. That last byte has the
- * address (start + len - 1), thus the highest page number is
- * (start + len - 1) / page_size. Since we want to include that last
- * page as well, the loop condition uses <=.
- */
- for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
- /* Byte position of the first byte in the range in this page. */
- /* starthere is an offset to the base address of the chip. */
- starthere = max(start, i * page_size);
- /* Length of bytes in the range in this page. */
- lenhere = min(start + len, (i + 1) * page_size) - starthere;
- for (j = 0; j < lenhere; j += chunksize) {
- toread = min(chunksize, lenhere - j);
- rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
- if (rc)
- break;
- }
- if (rc)
- break;
- }
-
- return rc;
-}
-
int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
if (!spi_programmer[spi_controller].read) {
@@ -1057,36 +191,6 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
}
/*
- * Program chip using byte programming. (SLOW!)
- * This is for chips which can only handle one byte writes
- * and for chips where memory mapped programming is impossible
- * (e.g. due to size constraints in IT87* for over 512 kB)
- */
-int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
-{
- int total_size = 1024 * flash->total_size;
- int i, result = 0;
-
- spi_disable_blockprotect();
- /* Erase first */
- printf("Erasing flash before programming... ");
- if (erase_flash(flash)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- printf("done.\n");
- for (i = 0; i < total_size; i++) {
- result = spi_byte_program(i, buf[i]);
- if (result)
- return 1;
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(10);
- }
-
- return 0;
-}
-
-/*
* Program chip using page (256 bytes) programming.
* Some SPI masters can't do this, they use single byte programming instead.
*/
@@ -1106,41 +210,3 @@ uint32_t spi_get_valid_read_addr(void)
/* Need to return BBAR for ICH chipsets. */
return 0;
}
-
-int spi_aai_write(struct flashchip *flash, uint8_t *buf)
-{
- uint32_t pos = 2, size = flash->total_size * 1024;
- unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
- int result;
-
- switch (spi_controller) {
-#if INTERNAL_SUPPORT == 1
- case SPI_CONTROLLER_WBSIO:
- fprintf(stderr, "%s: impossible with Winbond SPI masters,"
- " degrading to byte program\n", __func__);
- return spi_chip_write_1(flash, buf);
-#endif
- default:
- break;
- }
- if (erase_flash(flash)) {
- fprintf(stderr, "ERASE FAILED!\n");
- return -1;
- }
- /* FIXME: This will fail on ICH/VIA SPI. */
- result = spi_write_enable();
- if (result)
- return result;
- spi_send_command(6, 0, w, NULL);
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(5); /* SST25VF040B Tbp is max 10us */
- while (pos < size) {
- w[1] = buf[pos++];
- w[2] = buf[pos++];
- spi_send_command(3, 0, w, NULL);
- while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
- programmer_delay(5); /* SST25VF040B Tbp is max 10us */
- }
- spi_write_disable();
- return 0;
-}
diff --git a/spi25.c b/spi25.c
new file mode 100644
index 000000000..54121b081
--- /dev/null
+++ b/spi25.c
@@ -0,0 +1,992 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Contains the common SPI chip driver functions
+ */
+
+#include <string.h>
+#include "flash.h"
+#include "flashchips.h"
+#include "chipdrivers.h"
+#include "spi.h"
+
+void spi_prettyprint_status_register(struct flashchip *flash);
+
+static int spi_rdid(unsigned char *readarr, int bytes)
+{
+ const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
+ int ret;
+ int i;
+
+ ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr);
+ if (ret)
+ return ret;
+ printf_debug("RDID returned");
+ for (i = 0; i < bytes; i++)
+ printf_debug(" 0x%02x", readarr[i]);
+ printf_debug(". ");
+ return 0;
+}
+
+static int spi_rems(unsigned char *readarr)
+{
+ unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 };
+ uint32_t readaddr;
+ int ret;
+
+ ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
+ if (ret == SPI_INVALID_ADDRESS) {
+ /* Find the lowest even address allowed for reads. */
+ readaddr = (spi_get_valid_read_addr() + 1) & ~1;
+ cmd[1] = (readaddr >> 16) & 0xff,
+ cmd[2] = (readaddr >> 8) & 0xff,
+ cmd[3] = (readaddr >> 0) & 0xff,
+ ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
+ }
+ if (ret)
+ return ret;
+ printf_debug("REMS returned %02x %02x. ", readarr[0], readarr[1]);
+ return 0;
+}
+
+static int spi_res(unsigned char *readarr)
+{
+ unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
+ uint32_t readaddr;
+ int ret;
+
+ ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
+ if (ret == SPI_INVALID_ADDRESS) {
+ /* Find the lowest even address allowed for reads. */
+ readaddr = (spi_get_valid_read_addr() + 1) & ~1;
+ cmd[1] = (readaddr >> 16) & 0xff,
+ cmd[2] = (readaddr >> 8) & 0xff,
+ cmd[3] = (readaddr >> 0) & 0xff,
+ ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr);
+ }
+ if (ret)
+ return ret;
+ printf_debug("RES returned %02x. ", readarr[0]);
+ return 0;
+}
+
+int spi_write_enable(void)
+{
+ const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
+ int result;
+
+ /* Send WREN (Write Enable) */
+ result = spi_send_command(sizeof(cmd), 0, cmd, NULL);
+
+ if (result)
+ fprintf(stderr, "%s failed\n", __func__);
+
+ return result;
+}
+
+int spi_write_disable(void)
+{
+ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
+
+ /* Send WRDI (Write Disable) */
+ return spi_send_command(sizeof(cmd), 0, cmd, NULL);
+}
+
+static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
+{
+ unsigned char readarr[4];
+ uint32_t id1;
+ uint32_t id2;
+
+ if (spi_rdid(readarr, bytes))
+ return 0;
+
+ if (!oddparity(readarr[0]))
+ printf_debug("RDID byte 0 parity violation. ");
+
+ /* Check if this is a continuation vendor ID */
+ if (readarr[0] == 0x7f) {
+ if (!oddparity(readarr[1]))
+ printf_debug("RDID byte 1 parity violation. ");
+ id1 = (readarr[0] << 8) | readarr[1];
+ id2 = readarr[2];
+ if (bytes > 3) {
+ id2 <<= 8;
+ id2 |= readarr[3];
+ }
+ } else {
+ id1 = readarr[0];
+ id2 = (readarr[1] << 8) | readarr[2];
+ }
+
+ printf_debug("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id) {
+ /* Print the status register to tell the
+ * user about possible write protection.
+ */
+ spi_prettyprint_status_register(flash);
+
+ return 1;
+ }
+
+ /* Test if this is a pure vendor match. */
+ if (id1 == flash->manufacture_id &&
+ GENERIC_DEVICE_ID == flash->model_id)
+ return 1;
+
+ /* Test if there is any vendor ID. */
+ if (GENERIC_MANUF_ID == flash->manufacture_id &&
+ id1 != 0xff)
+ return 1;
+
+ return 0;
+}
+
+int probe_spi_rdid(struct flashchip *flash)
+{
+ return probe_spi_rdid_generic(flash, 3);
+}
+
+/* support 4 bytes flash ID */
+int probe_spi_rdid4(struct flashchip *flash)
+{
+ /* only some SPI chipsets support 4 bytes commands */
+ switch (spi_controller) {
+#if INTERNAL_SUPPORT == 1
+ case SPI_CONTROLLER_ICH7:
+ case SPI_CONTROLLER_ICH9:
+ case SPI_CONTROLLER_VIA:
+ case SPI_CONTROLLER_SB600:
+ case SPI_CONTROLLER_WBSIO:
+#endif
+#if FT2232_SPI_SUPPORT == 1
+ case SPI_CONTROLLER_FT2232:
+#endif
+#if DUMMY_SUPPORT == 1
+ case SPI_CONTROLLER_DUMMY:
+#endif
+#if BUSPIRATE_SPI_SUPPORT == 1
+ case SPI_CONTROLLER_BUSPIRATE:
+#endif
+#if DEDIPROG_SUPPORT == 1
+ case SPI_CONTROLLER_DEDIPROG:
+#endif
+ return probe_spi_rdid_generic(flash, 4);
+ default:
+ printf_debug("4b ID not supported on this SPI controller\n");
+ }
+
+ return 0;
+}
+
+int probe_spi_rems(struct flashchip *flash)
+{
+ unsigned char readarr[JEDEC_REMS_INSIZE];
+ uint32_t id1, id2;
+
+ if (spi_rems(readarr))
+ return 0;
+
+ id1 = readarr[0];
+ id2 = readarr[1];
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id) {
+ /* Print the status register to tell the
+ * user about possible write protection.
+ */
+ spi_prettyprint_status_register(flash);
+
+ return 1;
+ }
+
+ /* Test if this is a pure vendor match. */
+ if (id1 == flash->manufacture_id &&
+ GENERIC_DEVICE_ID == flash->model_id)
+ return 1;
+
+ /* Test if there is any vendor ID. */
+ if (GENERIC_MANUF_ID == flash->manufacture_id &&
+ id1 != 0xff)
+ return 1;
+
+ return 0;
+}
+
+int probe_spi_res(struct flashchip *flash)
+{
+ unsigned char readarr[3];
+ uint32_t id2;
+ const unsigned char allff[] = {0xff, 0xff, 0xff};
+ const unsigned char all00[] = {0x00, 0x00, 0x00};
+
+ /* Check if RDID is usable and does not return 0xff 0xff 0xff or
+ * 0x00 0x00 0x00. In that case, RES is pointless.
+ */
+ if (!spi_rdid(readarr, 3) && memcmp(readarr, allff, 3) &&
+ memcmp(readarr, all00, 3)) {
+ msg_cdbg("Ignoring RES in favour of RDID.\n");
+ return 0;
+ }
+ /* Check if REMS is usable and does not return 0xff 0xff or
+ * 0x00 0x00. In that case, RES is pointless.
+ */
+ if (!spi_rems(readarr) && memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
+ memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
+ msg_cdbg("Ignoring RES in favour of REMS.\n");
+ return 0;
+ }
+
+ if (spi_res(readarr))
+ return 0;
+
+ /* FIXME: Handle the case where RES gives a 2-byte response. */
+ id2 = readarr[0];
+ printf_debug("%s: id 0x%x\n", __func__, id2);
+ if (id2 != flash->model_id)
+ return 0;
+
+ /* Print the status register to tell the
+ * user about possible write protection.
+ */
+ spi_prettyprint_status_register(flash);
+ return 1;
+}
+
+uint8_t spi_read_status_register(void)
+{
+ const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
+ /* FIXME: No workarounds for driver/hardware bugs in generic code. */
+ unsigned char readarr[2]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
+ int ret;
+
+ /* Read Status Register */
+ ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
+ if (ret)
+ fprintf(stderr, "RDSR failed!\n");
+
+ return readarr[0];
+}
+
+/* Prettyprint the status register. Common definitions. */
+void spi_prettyprint_status_register_common(uint8_t status)
+{
+ printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
+ "%sset\n", (status & (1 << 5)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
+ "%sset\n", (status & (1 << 4)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
+ "%sset\n", (status & (1 << 3)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
+ "%sset\n", (status & (1 << 2)) ? "" : "not ");
+ printf_debug("Chip status register: Write Enable Latch (WEL) is "
+ "%sset\n", (status & (1 << 1)) ? "" : "not ");
+ printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
+ "%sset\n", (status & (1 << 0)) ? "" : "not ");
+}
+
+/* Prettyprint the status register. Works for
+ * ST M25P series
+ * MX MX25L series
+ */
+void spi_prettyprint_status_register_st_m25p(uint8_t status)
+{
+ printf_debug("Chip status register: Status Register Write Disable "
+ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 6 is "
+ "%sset\n", (status & (1 << 6)) ? "" : "not ");
+ spi_prettyprint_status_register_common(status);
+}
+
+void spi_prettyprint_status_register_sst25(uint8_t status)
+{
+ printf_debug("Chip status register: Block Protect Write Disable "
+ "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ printf_debug("Chip status register: Auto Address Increment Programming "
+ "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
+ spi_prettyprint_status_register_common(status);
+}
+
+/* Prettyprint the status register. Works for
+ * SST 25VF016
+ */
+void spi_prettyprint_status_register_sst25vf016(uint8_t status)
+{
+ const char *bpt[] = {
+ "none",
+ "1F0000H-1FFFFFH",
+ "1E0000H-1FFFFFH",
+ "1C0000H-1FFFFFH",
+ "180000H-1FFFFFH",
+ "100000H-1FFFFFH",
+ "all", "all"
+ };
+ spi_prettyprint_status_register_sst25(status);
+ printf_debug("Resulting block protection : %s\n",
+ bpt[(status & 0x1c) >> 2]);
+}
+
+void spi_prettyprint_status_register_sst25vf040b(uint8_t status)
+{
+ const char *bpt[] = {
+ "none",
+ "0x70000-0x7ffff",
+ "0x60000-0x7ffff",
+ "0x40000-0x7ffff",
+ "all blocks", "all blocks", "all blocks", "all blocks"
+ };
+ spi_prettyprint_status_register_sst25(status);
+ printf_debug("Resulting block protection : %s\n",
+ bpt[(status & 0x1c) >> 2]);
+}
+
+void spi_prettyprint_status_register(struct flashchip *flash)
+{
+ uint8_t status;
+
+ status = spi_read_status_register();
+ printf_debug("Chip status register is %02x\n", status);
+ switch (flash->manufacture_id) {
+ case ST_ID:
+ if (((flash->model_id & 0xff00) == 0x2000) ||
+ ((flash->model_id & 0xff00) == 0x2500))
+ spi_prettyprint_status_register_st_m25p(status);
+ break;
+ case MX_ID:
+ if ((flash->model_id & 0xff00) == 0x2000)
+ spi_prettyprint_status_register_st_m25p(status);
+ break;
+ case SST_ID:
+ switch (flash->model_id) {
+ case 0x2541:
+ spi_prettyprint_status_register_sst25vf016(status);
+ break;
+ case 0x8d:
+ case 0x258d:
+ spi_prettyprint_status_register_sst25vf040b(status);
+ break;
+ default:
+ spi_prettyprint_status_register_sst25(status);
+ break;
+ }
+ break;
+ }
+}
+
+int spi_chip_erase_60(struct flashchip *flash)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_CE_60_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_CE_60 },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_disable_blockprotect();
+ if (result) {
+ fprintf(stderr, "spi_disable_blockprotect failed\n");
+ return result;
+ }
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution\n",
+ __func__);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 1-85 s, so wait in 1 s steps.
+ */
+ /* FIXME: We assume spi_read_status_register will never fail. */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(1000 * 1000);
+ if (check_erased_range(flash, 0, flash->total_size * 1024)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int spi_chip_erase_c7(struct flashchip *flash)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_CE_C7_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_CE_C7 },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_disable_blockprotect();
+ if (result) {
+ fprintf(stderr, "spi_disable_blockprotect failed\n");
+ return result;
+ }
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution\n", __func__);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 1-85 s, so wait in 1 s steps.
+ */
+ /* FIXME: We assume spi_read_status_register will never fail. */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(1000 * 1000);
+ if (check_erased_range(flash, 0, flash->total_size * 1024)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int spi_chip_erase_60_c7(struct flashchip *flash)
+{
+ int result;
+ result = spi_chip_erase_60(flash);
+ if (result) {
+ printf_debug("spi_chip_erase_60 failed, trying c7\n");
+ result = spi_chip_erase_c7(flash);
+ }
+ return result;
+}
+
+int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_BE_52_OUTSIZE,
+ .writearr = (const unsigned char[]){
+ JEDEC_BE_52,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr & 0xff)
+ },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 100-4000 ms, so wait in 100 ms steps.
+ */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(100 * 1000);
+ if (check_erased_range(flash, addr, blocklen)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+/* Block size is usually
+ * 64k for Macronix
+ * 32k for SST
+ * 4-32k non-uniform for EON
+ */
+int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_BE_D8_OUTSIZE,
+ .writearr = (const unsigned char[]){
+ JEDEC_BE_D8,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr & 0xff)
+ },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 100-4000 ms, so wait in 100 ms steps.
+ */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(100 * 1000);
+ if (check_erased_range(flash, addr, blocklen)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+/* Block size is usually
+ * 4k for PMC
+ */
+int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_BE_D7_OUTSIZE,
+ .writearr = (const unsigned char[]){
+ JEDEC_BE_D7,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr & 0xff)
+ },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 100-4000 ms, so wait in 100 ms steps.
+ */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(100 * 1000);
+ if (check_erased_range(flash, addr, blocklen)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int spi_chip_erase_d8(struct flashchip *flash)
+{
+ int i, rc = 0;
+ int total_size = flash->total_size * 1024;
+ int erase_size = 64 * 1024;
+
+ spi_disable_blockprotect();
+
+ printf("Erasing chip: \n");
+
+ for (i = 0; i < total_size / erase_size; i++) {
+ rc = spi_block_erase_d8(flash, i * erase_size, erase_size);
+ if (rc) {
+ fprintf(stderr, "Error erasing block at 0x%x\n", i);
+ break;
+ }
+ }
+
+ printf("\n");
+
+ return rc;
+}
+
+/* Sector size is usually 4k, though Macronix eliteflash has 64k */
+int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_SE_OUTSIZE,
+ .writearr = (const unsigned char[]){
+ JEDEC_SE,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr & 0xff)
+ },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ return result;
+ }
+ /* Wait until the Write-In-Progress bit is cleared.
+ * This usually takes 15-800 ms, so wait in 10 ms steps.
+ */
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(10 * 1000);
+ if (check_erased_range(flash, addr, blocklen)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
+ fprintf(stderr, "%s called with incorrect arguments\n",
+ __func__);
+ return -1;
+ }
+ return spi_chip_erase_60(flash);
+}
+
+int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen)
+{
+ if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
+ fprintf(stderr, "%s called with incorrect arguments\n",
+ __func__);
+ return -1;
+ }
+ return spi_chip_erase_c7(flash);
+}
+
+int spi_write_status_enable(void)
+{
+ const unsigned char cmd[JEDEC_EWSR_OUTSIZE] = { JEDEC_EWSR };
+ int result;
+
+ /* Send EWSR (Enable Write Status Register). */
+ result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL);
+
+ if (result)
+ fprintf(stderr, "%s failed\n", __func__);
+
+ return result;
+}
+
+/*
+ * This is according the SST25VF016 datasheet, who knows it is more
+ * generic that this...
+ */
+int spi_write_status_register(int status)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
+ .writecnt = JEDEC_EWSR_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_EWSR },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_WRSR_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WRSR, (unsigned char) status },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution\n",
+ __func__);
+ }
+ return result;
+}
+
+int spi_byte_program(int addr, uint8_t databyte)
+{
+ int result;
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE,
+ .writearr = (const unsigned char[]){
+ JEDEC_BYTE_PROGRAM,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr & 0xff),
+ databyte
+ },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ }
+ return result;
+}
+
+int spi_nbyte_program(int addr, uint8_t *bytes, int len)
+{
+ int result;
+ /* FIXME: Switch to malloc based on len unless that kills speed. */
+ unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = {
+ JEDEC_BYTE_PROGRAM,
+ (addr >> 16) & 0xff,
+ (addr >> 8) & 0xff,
+ (addr >> 0) & 0xff,
+ };
+ struct spi_command cmds[] = {
+ {
+ .writecnt = JEDEC_WREN_OUTSIZE,
+ .writearr = (const unsigned char[]){ JEDEC_WREN },
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len,
+ .writearr = cmd,
+ .readcnt = 0,
+ .readarr = NULL,
+ }, {
+ .writecnt = 0,
+ .writearr = NULL,
+ .readcnt = 0,
+ .readarr = NULL,
+ }};
+
+ if (!len) {
+ fprintf(stderr, "%s called for zero-length write\n", __func__);
+ return 1;
+ }
+ if (len > 256) {
+ fprintf(stderr, "%s called for too long a write\n", __func__);
+ return 1;
+ }
+
+ memcpy(&cmd[4], bytes, len);
+
+ result = spi_send_multicommand(cmds);
+ if (result) {
+ fprintf(stderr, "%s failed during command execution at address 0x%x\n",
+ __func__, addr);
+ }
+ return result;
+}
+
+int spi_disable_blockprotect(void)
+{
+ uint8_t status;
+ int result;
+
+ status = spi_read_status_register();
+ /* If there is block protection in effect, unprotect it first. */
+ if ((status & 0x3c) != 0) {
+ printf_debug("Some block protection in effect, disabling\n");
+ result = spi_write_status_register(status & ~0x3c);
+ if (result) {
+ fprintf(stderr, "spi_write_status_register failed\n");
+ return result;
+ }
+ }
+ return 0;
+}
+
+int spi_nbyte_read(int address, uint8_t *bytes, int len)
+{
+ const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
+ JEDEC_READ,
+ (address >> 16) & 0xff,
+ (address >> 8) & 0xff,
+ (address >> 0) & 0xff,
+ };
+
+ /* Send Read */
+ return spi_send_command(sizeof(cmd), len, cmd, bytes);
+}
+
+/*
+ * Read a complete flash chip.
+ * Each page is read separately in chunks with a maximum size of chunksize.
+ */
+int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize)
+{
+ int rc = 0;
+ int i, j, starthere, lenhere;
+ int page_size = flash->page_size;
+ int toread;
+
+ /* Warning: This loop has a very unusual condition and body.
+ * The loop needs to go through each page with at least one affected
+ * byte. The lowest page number is (start / page_size) since that
+ * division rounds down. The highest page number we want is the page
+ * where the last byte of the range lives. That last byte has the
+ * address (start + len - 1), thus the highest page number is
+ * (start + len - 1) / page_size. Since we want to include that last
+ * page as well, the loop condition uses <=.
+ */
+ for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
+ /* Byte position of the first byte in the range in this page. */
+ /* starthere is an offset to the base address of the chip. */
+ starthere = max(start, i * page_size);
+ /* Length of bytes in the range in this page. */
+ lenhere = min(start + len, (i + 1) * page_size) - starthere;
+ for (j = 0; j < lenhere; j += chunksize) {
+ toread = min(chunksize, lenhere - j);
+ rc = spi_nbyte_read(starthere + j, buf + starthere - start + j, toread);
+ if (rc)
+ break;
+ }
+ if (rc)
+ break;
+ }
+
+ return rc;
+}
+
+/*
+ * Program chip using byte programming. (SLOW!)
+ * This is for chips which can only handle one byte writes
+ * and for chips where memory mapped programming is impossible
+ * (e.g. due to size constraints in IT87* for over 512 kB)
+ */
+int spi_chip_write_1(struct flashchip *flash, uint8_t *buf)
+{
+ int total_size = 1024 * flash->total_size;
+ int i, result = 0;
+
+ spi_disable_blockprotect();
+ /* Erase first */
+ printf("Erasing flash before programming... ");
+ if (erase_flash(flash)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ printf("done.\n");
+ for (i = 0; i < total_size; i++) {
+ result = spi_byte_program(i, buf[i]);
+ if (result)
+ return 1;
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(10);
+ }
+
+ return 0;
+}
+
+int spi_aai_write(struct flashchip *flash, uint8_t *buf)
+{
+ uint32_t pos = 2, size = flash->total_size * 1024;
+ unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]};
+ int result;
+
+ switch (spi_controller) {
+#if INTERNAL_SUPPORT == 1
+ case SPI_CONTROLLER_WBSIO:
+ fprintf(stderr, "%s: impossible with Winbond SPI masters,"
+ " degrading to byte program\n", __func__);
+ return spi_chip_write_1(flash, buf);
+#endif
+ default:
+ break;
+ }
+ if (erase_flash(flash)) {
+ fprintf(stderr, "ERASE FAILED!\n");
+ return -1;
+ }
+ /* FIXME: This will fail on ICH/VIA SPI. */
+ result = spi_write_enable();
+ if (result)
+ return result;
+ spi_send_command(6, 0, w, NULL);
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(5); /* SST25VF040B Tbp is max 10us */
+ while (pos < size) {
+ w[1] = buf[pos++];
+ w[2] = buf[pos++];
+ spi_send_command(3, 0, w, NULL);
+ while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
+ programmer_delay(5); /* SST25VF040B Tbp is max 10us */
+ }
+ spi_write_disable();
+ return 0;
+}
diff --git a/sst28sf040.c b/sst28sf040.c
index f253e39ea..bbb9d568d 100644
--- a/sst28sf040.c
+++ b/sst28sf040.c
@@ -21,6 +21,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
#define AUTO_PG_ERASE1 0x20
#define AUTO_PG_ERASE2 0xD0
diff --git a/sst49lfxxxc.c b/sst49lfxxxc.c
index a65450e5a..9f9ee308c 100644
--- a/sst49lfxxxc.c
+++ b/sst49lfxxxc.c
@@ -22,6 +22,7 @@
#include <stdlib.h>
#include "flash.h"
+#include "chipdrivers.h"
#define SECTOR_ERASE 0x30
#define BLOCK_ERASE 0x20
diff --git a/sst_fwhub.c b/sst_fwhub.c
index 75d9e05c6..9819ceedd 100644
--- a/sst_fwhub.c
+++ b/sst_fwhub.c
@@ -25,6 +25,7 @@
#include <stdlib.h>
#include <string.h>
#include "flash.h"
+#include "chipdrivers.h"
// I need that Berkeley bit-map printer
void print_sst_fwhub_status(uint8_t status)
diff --git a/stm50flw0x0x.c b/stm50flw0x0x.c
index 3b564365c..7095aecef 100644
--- a/stm50flw0x0x.c
+++ b/stm50flw0x0x.c
@@ -31,6 +31,7 @@
#include <stdlib.h>
#include "flash.h"
#include "flashchips.h"
+#include "chipdrivers.h"
static void wait_stm50flw0x0x(chipaddr bios)
{
diff --git a/w29ee011.c b/w29ee011.c
index de9a547cc..63cf4fc4a 100644
--- a/w29ee011.c
+++ b/w29ee011.c
@@ -20,6 +20,7 @@
#include <string.h>
#include "flash.h"
+#include "chipdrivers.h"
int probe_w29ee011(struct flashchip *flash)
{
diff --git a/w39v040c.c b/w39v040c.c
index 853419ac8..20e53fa7b 100644
--- a/w39v040c.c
+++ b/w39v040c.c
@@ -19,6 +19,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
int probe_w39v040c(struct flashchip *flash)
{
diff --git a/w39v080fa.c b/w39v080fa.c
index 8e846dc30..0163766ee 100644
--- a/w39v080fa.c
+++ b/w39v080fa.c
@@ -19,6 +19,7 @@
*/
#include "flash.h"
+#include "chipdrivers.h"
static int unlock_block_winbond_fwhub(struct flashchip *flash, int offset)
{
diff --git a/wbsio_spi.c b/wbsio_spi.c
index 922aff189..ca3932218 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -20,6 +20,7 @@
#include <string.h>
#include "flash.h"
+#include "chipdrivers.h"
#include "spi.h"
#define WBSIO_PORT1 0x2e