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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-03-27 12:15:09 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-04-24 20:18:58 +0000 |
| commit | 124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b (patch) | |
| tree | 980f498681fcc053ec1e591e22bb16afbef0a191 /chipset_enable.c | |
| parent | 3f7e3419887c6d37330387f8e32c86ba47bdf70c (diff) | |
| download | flashrom-124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b.tar.gz flashrom-124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b.tar.bz2 flashrom-124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b.zip | |
Fix whitespace errors
Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 8243455b4..9c88695f1 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1117,7 +1117,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name) /* * Geode systems write protect the BIOS via RCONFs (cache settings similar - * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. + * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. * * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. * To enable write to NOR Boot flash for the benefit of systems that have such |