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| author | Edward O'Callaghan <quasisec@google.com> | 2022-08-12 16:37:45 +1000 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-09-07 02:57:37 +0000 |
| commit | 2c520b4afa9bc7d51b9cec2b3cd4a2c325aecb1e (patch) | |
| tree | 35dfef772260d1e29b0c71cab3db9021ae43abef /chipset_enable.c | |
| parent | 162b997f2fb36d44640c6ca97baee328550c0869 (diff) | |
| download | flashrom-2c520b4afa9bc7d51b9cec2b3cd4a2c325aecb1e.tar.gz flashrom-2c520b4afa9bc7d51b9cec2b3cd4a2c325aecb1e.tar.bz2 flashrom-2c520b4afa9bc7d51b9cec2b3cd4a2c325aecb1e.zip | |
chipset_enable.c: plumb programmer_cfg into sb600 and ich init
Change-Id: Ic25014cbb983bda6e949bc62e30f2cca51f57a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index d8aa53dd7..e205a83d4 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -428,7 +428,7 @@ static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct break; } - char *idsel = extract_programmer_param_str(NULL, "fwh_idsel"); /* TODO(quasisec): pass prog_param */ + char *idsel = extract_programmer_param_str(cfg, "fwh_idsel"); if (idsel && strlen(idsel)) { if (!implemented) { msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); @@ -816,7 +816,7 @@ static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev void *spibar = rcrb + spibar_offset; /* This adds BUS_SPI */ - int ret_spi = ich_init_spi(NULL, spibar, ich_generation); /* TODO(quasisec): pass prog_param */ + int ret_spi = ich_init_spi(cfg, spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -960,7 +960,7 @@ static int enable_flash_pch100_or_c620(const struct programmer_cfg *cfg, msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); /* This adds BUS_SPI */ - const int ret_spi = ich_init_spi(NULL, spibar, pch_generation); /* TODO(quasisec): pass prog_param */ + const int ret_spi = ich_init_spi(cfg, spibar, pch_generation); if (ret_spi != ERROR_FATAL) { if (ret_bc || ret_spi) ret = ERROR_NONFATAL; @@ -1077,7 +1077,7 @@ static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_ */ enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); - int ret_spi = ich_init_spi(NULL, spibar, ich_generation); /* TODO(quasisec): pass prog_param */ + int ret_spi = ich_init_spi(cfg, spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -1407,7 +1407,7 @@ static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev * internal_buses_supported &= BUS_LPC | BUS_FWH; - ret = sb600_probe_spi(NULL, dev); /* TODO(quasisec): pass prog_param */ + ret = sb600_probe_spi(cfg, dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); |