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authormelvyn2 <melvyn2@brcok.tk>2021-10-30 16:02:22 -0700
committerNico Huber <nico.h@gmx.de>2021-11-17 12:24:47 +0000
commit7692a2ee78020d8d3a52bf45b9d57ed5d98499e0 (patch)
tree3bc0c18e8acf643cf75cf0170912f39d0fdc3c85 /chipset_enable.c
parent93b01904db607ef8169047e68e376dcda1bd7fbe (diff)
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chipset_enable.c: Mark Intel Z390 as DEP
Tested read/write on GIGABYTE Z390 AORUS MASTER, incl. ME region with me_cleaner. Change-Id: If14d45c144bb32a1d1046185d4476ea29e4d0912 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: melvyn2 <melvyn2@brcok.tk> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58774 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'chipset_enable.c')
-rw-r--r--chipset_enable.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/chipset_enable.c b/chipset_enable.c
index 26db472ad..2e4bb1e4a 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2103,7 +2103,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk},
{0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300},
{0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300},
- {0x8086, 0xa305, B_S, NT, "Intel", "Z390", enable_flash_pch300},
+ {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300},
{0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300},
{0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300},
{0x8086, 0xa309, B_S, NT, "Intel", "C246", enable_flash_pch300},