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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 10:50:40 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2021-05-18 12:54:04 +0000 |
| commit | fbc38c71589910876466fd385a1f64f1c0c40eb7 (patch) | |
| tree | ca528c619bde6fd6896928c4422f18d8c9f49323 /chipset_enable.c | |
| parent | 16c62a791d0a311bb040812b03c33881ab641a8e (diff) | |
| download | flashrom-fbc38c71589910876466fd385a1f64f1c0c40eb7.tar.gz flashrom-fbc38c71589910876466fd385a1f64f1c0c40eb7.tar.bz2 flashrom-fbc38c71589910876466fd385a1f64f1c0c40eb7.zip | |
chipset_enable.c: Add Gemini Lake eSPI PCI device ID
Taken from coreboot `PCI_DEVICE_ID_INTEL_GLK_ESPI` macro, untested.
Change-Id: Ie34527e56edcba4982f17b8e0aef0fc4280a52bc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Diffstat (limited to 'chipset_enable.c')
| -rw-r--r-- | chipset_enable.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 025203cb5..cdd51aefe 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2084,6 +2084,7 @@ const struct penable chipset_enables[] = { {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, |