spi25_statusreg,flashchips: add SR2 read/write support

This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.

Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.

BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom -{r,w,E}
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands

Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 3 insertions, 0 deletions

diff --git a/flash.h b/flash.h
index f1a8b340e..cd40fa3ff 100644
--- a/flash.h
+++ b/flash.h
@@ -140,6 +140,9 @@ enum write_granularity {
 #define FEATURE_ERASED_ZERO	(1 << 17)
 #define FEATURE_NO_ERASE	(1 << 18)
 
+#define FEATURE_WRSR_EXT	(1 << 19)
+#define FEATURE_WRSR2		(1 << 20)
+
 #define ERASED_VALUE(flash)	(((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
 
 enum test_state {