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| author | Thomas Heijligen <thomas.heijligen@secunet.com> | 2022-06-30 10:29:44 +0200 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-07-17 22:43:56 +0000 |
| commit | df0bbf07dec6fcfe8f03f2a0774630a9135c2711 (patch) | |
| tree | d54a4695d994a5ebf245b92f226f811f59d58d99 /flashrom.8.tmpl | |
| parent | 494bedae23c547e0a3e8f86a5a69cf4b05bd1586 (diff) | |
| download | flashrom-df0bbf07dec6fcfe8f03f2a0774630a9135c2711.tar.gz flashrom-df0bbf07dec6fcfe8f03f2a0774630a9135c2711.tar.bz2 flashrom-df0bbf07dec6fcfe8f03f2a0774630a9135c2711.zip | |
Rename lspcon_i2c_spi to parade_lspcon
The chip targeted by the `lspcon_i2c_spi` programmer is a Parade PS175.
Rename the programmer to match the chips vendor / family instead of the
generic LSPCON protocol. Remove the `_i2c_spi` ending in preparation to
become an opaque master. The chip is visible on an Acer Chromebox CXI4.
https://www.paradetech.com/products/ps175/
https://www.acer.com/ac/en/US/content/series/acerchromeboxcxi4
TEST: `make CONFIG_PARADE_LSPCON=yes` and
`meson build -Dconfig_parade_lspcon=true` produces flashrom
binaries with the parade_lspcon programmer included.
Change-Id: I9148be6d9162c1722ff739929ca5e181b628dd57
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/65547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'flashrom.8.tmpl')
| -rw-r--r-- | flashrom.8.tmpl | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index b3d44636b..362b14a79 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -427,7 +427,7 @@ bitbanging adapter) .sp .BR "* realtek_mst_i2c_spi" " (for SPI flash ROMs attached to Realtek DisplayPort hubs accessible through I2C)" .sp -.BR "* lspcon_i2c_spi" " (for SPI flash ROMs attached to Parade Technologies LSPCONs)" +.BR "* parade_lspcon" " (for SPI flash ROMs attached to Parade Technologies LSPCONs (PS175))" .sp Some programmers have optional or mandatory parameters which are described in detail in the @@ -1521,7 +1521,7 @@ syntax where \fBfrequency\fP is the SPI clock frequency in kHz. If the passed frequency is not supported by the adapter the nearest lower supported frequency will be used. .SS -.BR "realtek_mst_i2c_spi " and " lspcon_i2c_spi " programmers +.BR "realtek_mst_i2c_spi " and " parade_lspcon " programmers .IP These programmers tunnel SPI commands through I2C-connected devices. The I2C bus over which communication occurs must be specified either by device path @@ -1532,7 +1532,7 @@ with the \fBdevpath\fP option: or by a bus number with the \fBbus\fP option, which implies a device path like /dev/i2c-N where N is the specified bus number: .sp -.B " flashrom \-p lspcon_i2c_spi:bus=8" +.B " flashrom \-p parade_lspcon:bus=8" .SS .BR "realtek_mst_i2c_spi " programmer @@ -1565,11 +1565,12 @@ flash): .br .B " flashrom -p realtek_mst_i2c_spi:bus=0,enter-isp=0,reset-mcu=1 -w new.bin" .SS -.BR "lspcon_i2c_spi " programmer +.BR "parade_lspcon " programmer .IP This programmer supports SPI flash programming for chips attached to Parade -Technologies DisplayPort-to-HDMI level shifter/protocol converters (LSPCONs). -Communication to the SPI flash is tunneled through the LSPCON over I2C. +Technologies DisplayPort-to-HDMI level shifter/protocol converters (LSPCONs), +e.g. the PS175. Communication to the SPI flash is tunneled through the LSPCON +over I2C. .SH EXAMPLES To back up and update your BIOS, run @@ -1651,7 +1652,7 @@ permissions are set. .B ogp needs PCI configuration space read access and raw memory access. .sp -.BR realtek_mst_i2c_spi " and " lspcon_i2c_spi +.BR realtek_mst_i2c_spi " and " parade_lspcon need userspace access to the selected I2C bus. .sp On OpenBSD, you can obtain raw access permission by setting |