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| author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2021-11-08 00:05:12 +0200 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-05-12 02:56:07 +0000 |
| commit | fa2cf255ec587f02baf987f21ab6d01de5db8c8e (patch) | |
| tree | 00b1f34acf694f2912d7d5022acb12e1f31d64fc /flashrom.8.tmpl | |
| parent | c829a48e198d723f0e6ae1ff6d6f820eb085711d (diff) | |
| download | flashrom-fa2cf255ec587f02baf987f21ab6d01de5db8c8e.tar.gz flashrom-fa2cf255ec587f02baf987f21ab6d01de5db8c8e.tar.bz2 flashrom-fa2cf255ec587f02baf987f21ab6d01de5db8c8e.zip | |
dummyflasher: add SR2 and SR3 emulation harness
Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
TEST=check how input value affects status registers of emulated chip
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x12 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x1234 |
grep 'Initial status register'
flashrom -V -p dummy:emulate=W25Q128FV,spi_status=0x123456 |
grep 'Initial status register'
Mind that at this point there are no chips that emulate more than one
status register.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/59072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'flashrom.8.tmpl')
| -rw-r--r-- | flashrom.8.tmpl | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 84e0fba32..0f7bc9748 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -816,7 +816,10 @@ You can specify the initial content of the chip's status register with the .sp syntax where .B content -is an 8-bit hexadecimal value. +is a hexadecimal value of up to 24 bits. For example, 0x332211 assigns 0x11 to +SR1, 0x22 to SR2 and 0x33 to SR3. Shorter value is padded to 24 bits with +zeroes on the left. See datasheet for chosen chip for details about the +registers content. .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ |