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| author | sibradzic <5964548+sibradzic@users.noreply.github.com> | 2020-02-14 17:15:02 +0900 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-03-09 09:22:18 +0000 |
| commit | a43e44b6abbe8381be3f3dd20a430973cf8b8ab5 (patch) | |
| tree | 6931bad62352fa8c8e12cd3d24446fa6b273bdbf /ft2232_spi.c | |
| parent | ba6575de82f091b97ea0f2efcf2f79ef3739d64f (diff) | |
| download | flashrom-a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.tar.gz flashrom-a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.tar.bz2 flashrom-a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.zip | |
ft2232_spi: Fix broken GPIOL cs_bits state (#126)
This only sets 3rd CS# bit be asserted during read/write operations.
Tested and confirmed working on 4232H & PicoTap ft2232 programmers
against MX25R6435F & S25FL128S chips.
Signed-off-by: Samir Ibradzic <sibradzic@gmail.com>
Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'ft2232_spi.c')
| -rw-r--r-- | ft2232_spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ft2232_spi.c b/ft2232_spi.c index 3e4dc9e44..1a5b2feb4 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -495,7 +495,7 @@ static int ft2232_spi_send_command(struct flashctx *flash, */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = ~ 0x08 & cs_bits; /* assert CS (3rd) bit only */ buf[i++] = pindir; if (writecnt) { |