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| author | Nico Huber <nico.h@gmx.de> | 2021-06-20 14:37:55 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-06-25 12:50:10 +0000 |
| commit | c3f765917d0e5ceb3c576ba3f3701413b92b26dc (patch) | |
| tree | f7d03cbf28c681beb66afdb9ec11bbb62a7a4f44 /ft2232_spi.c | |
| parent | 6518cf352d65330efdb8e30358a35a250d4222ba (diff) | |
| download | flashrom-c3f765917d0e5ceb3c576ba3f3701413b92b26dc.tar.gz flashrom-c3f765917d0e5ceb3c576ba3f3701413b92b26dc.tar.bz2 flashrom-c3f765917d0e5ceb3c576ba3f3701413b92b26dc.zip | |
Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)"
This reverts commit a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.
Nothing was broken. So this breaks everything. Well, actually only
the `csgpiol` parameter. But that is very obvious.
`csgpiol` was added to use a GPIO pin as /CS. But this change impli-
citly hardcoded /CS to ADBUS3.
Change-Id: I9ecdfe227585dda74658c16c96a57dd42d1d78b4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/55693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'ft2232_spi.c')
| -rw-r--r-- | ft2232_spi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ft2232_spi.c b/ft2232_spi.c index 78bf0fc6d..44975db35 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -226,7 +226,7 @@ static int ft2232_spi_send_multicommand(const struct flashctx *flash, struct spi msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = ~ 0x08 & spi_data->cs_bits; /* assert CS (3rd) bit only */ + buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */ buf[i++] = spi_data->pindir; /* WREN, OP(PROGRAM, ERASE), ADDR, DATA */ |