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| author | Subrata Banik <subratabanik@google.com> | 2022-04-11 12:00:19 +0000 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-05-03 05:02:38 +0000 |
| commit | 8ce92004441f7a39733a5a91729584e006679829 (patch) | |
| tree | c839d786c7ab45027aaba1501212660261465a3a /ichspi.c | |
| parent | 3f93a14fc36b6724566e42429f620d13b7171f17 (diff) | |
| download | flashrom-8ce92004441f7a39733a5a91729584e006679829.tar.gz flashrom-8ce92004441f7a39733a5a91729584e006679829.tar.bz2 flashrom-8ce92004441f7a39733a5a91729584e006679829.zip | |
ichspi: Drop unused `_pprint_reg` macro
This patch drops `_pprint_reg` macro as `pprint_reg` macro is
now able to call into msg_pdbg().
BUG=b:223630977
TEST=Able to display HSFS register offset properly as below
BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled
Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPIBAR = 0x00007fce5a270000 (phys = 0xfe010000)
0x04: 0xf000 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1,
FLOCKDN=1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee7a23447de38423b61008b3242d28ce553ae0a2
Reviewed-on: https://review.coreboot.org/c/flashrom/+/63549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'ichspi.c')
| -rw-r--r-- | ichspi.c | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -412,8 +412,7 @@ static void prettyprint_opcodes(OPCODES *ops) ops->preop[1]); } -#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) -#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit) >> reg##_##bit##_OFF) static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen) { |