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| author | Sergii Dmytruk <sergii.dmytruk@3mdeb.com> | 2022-07-24 17:11:05 +0300 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2022-11-19 06:56:11 +0000 |
| commit | 125a328b4d8445f41c9fdde9e51c1b2bb40ad72e (patch) | |
| tree | ebc90fd1c88be2924d9d034bd171312fe829229e /include/spi.h | |
| parent | f32f5e31d99531ee61bd31c64f41cc4baee68d57 (diff) | |
| download | flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.tar.gz flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.tar.bz2 flashrom-125a328b4d8445f41c9fdde9e51c1b2bb40ad72e.zip | |
spi25_statusreg: support reading/writing configuration register
One more variation of registers.
This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.
Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'include/spi.h')
| -rw-r--r-- | include/spi.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/spi.h b/include/spi.h index c77866c41..505aecd01 100644 --- a/include/spi.h +++ b/include/spi.h @@ -177,6 +177,11 @@ #define JEDEC_WRSCUR_OUTSIZE 0x01 #define JEDEC_WRSCUR_INSIZE 0x00 +/* Read Configuration Register */ +#define JEDEC_RDCR 0x15 +#define JEDEC_RDCR_OUTSIZE 0x01 +#define JEDEC_RDCR_INSIZE 0x01 + /* Enter 4-byte Address Mode */ #define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 |