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authorElyes HAOUAS <ehaouas@noos.fr>2018-03-27 12:15:09 +0200
committerNico Huber <nico.h@gmx.de>2018-04-24 20:18:58 +0000
commit124ef38f7afc61ad7c713c22aad7c5c7f79bdb9b (patch)
tree980f498681fcc053ec1e591e22bb16afbef0a191 /jedec.c
parent3f7e3419887c6d37330387f8e32c86ba47bdf70c (diff)
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Fix whitespace errors
Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'jedec.c')
-rw-r--r--jedec.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/jedec.c b/jedec.c
index af13876a5..bd3af2f7d 100644
--- a/jedec.c
+++ b/jedec.c
@@ -68,7 +68,7 @@ void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst)
* The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
* but experiments show that 2 ms are already enough. Pick a safety factor
* of 4 and use an 8 ms delay.
- * Given that erase is slow on all chips, it is recommended to use
+ * Given that erase is slow on all chips, it is recommended to use
* toggle_ready_jedec_slow in erase functions.
*/
static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst)