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| author | Neil Armstrong <narmstrong@baylibre.com> | 2021-01-27 12:13:35 +0000 |
|---|---|---|
| committer | Anastasia Klimchuk <aklm@chromium.org> | 2023-09-16 08:41:46 +0000 |
| commit | aa468cf0bd49e1da193b47937193b958f646430e (patch) | |
| tree | 276d571960f0ff3ebc2915adfc64ca454a92b897 /mcp6x_spi.c | |
| parent | 761746754484843c41a2fc1d672e8848cc7afa6a (diff) | |
| download | flashrom-aa468cf0bd49e1da193b47937193b958f646430e.tar.gz flashrom-aa468cf0bd49e1da193b47937193b958f646430e.tar.bz2 flashrom-aa468cf0bd49e1da193b47937193b958f646430e.zip | |
flashchips: add definition of the XT25F02E SPI NOR flash
This adds definition of the XT25F02E 2MBit SPI NOR Flash
from XTX Technology Limited.
Tested (Probe, Erase, Write, Read) with a VL805 USB3.0 bridge.
Datasheet:
https://datasheet.lcsc.com/lcsc/2006091008_XTX-XT25F02EDTIGT_C596313.pdf
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Change-Id: I295633c448c05520e4a6aa09c08bd7c9f2346d54
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/50263
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'mcp6x_spi.c')
0 files changed, 0 insertions, 0 deletions